鎳金屬矽化物與堆疊式結構對閘極氧化層可靠度之研究

Abstract

當元件的尺寸持續的縮小，短通道效應將會變嚴重，因此需要很高劑量的通道摻雜才能達到控制元件臨界電壓的目的。但是，載子的遷移率將會因此而減低且影響到元件特性。為了解決這個問題，將會利用適當功函數的金屬閘極來控制元件的臨界電壓。但是，金屬閘極會和自我對準製程有整合上的困難。最近，完全矽化鎳閘極被廣泛地研究來取代金屬閘極，金屬矽化鎳閘極具有低電阻率、消除多晶矽閘極空乏現象、可調變的功函數以及整合容易等優點，但是鎳金屬是否影響到閘極氧化層的可靠度將是一個關鍵問題。 在本論文中我們研究矽化鎳閘極的氧化層可靠度，利用不同的溫度和結構去完成矽化鎳閘極，我們發現，對於無摻雜的複晶矽跟非晶矽結構而言，鎳穿入氧化層的含量會隨著退火溫度而增加，因此鎳金屬在高溫退火後對氧化層造成很嚴重的損傷；而對於n型矽化鎳閘極而言，即使經過800oC退火後，其氧化層的可靠度仍然是穩定的，這是因為在退火過程中，雜質和鎳金屬發生反應，因而阻擋了鎳金屬在矽中的擴散；另外，從ＴＥＭ照片上，可觀察出矽化鎳的均勻性和晶粒大小隨著溫度而增加。再由平帶電壓的漂移，我們發現n型矽化鎳閘極功函數隨著溫度而改變。 此外我們還利用n型非晶矽/複晶矽和複晶矽/n型非晶矽的堆疊式結構來完成矽化鎳金屬閘極。然而，在高溫退火後，還是有多量的鎳金屬穿入氧化層中，使得氧化層的電性變差。這是因為鎳金屬含量相當多，所以能被非晶矽和複晶矽間的介面阻擋的鎳金屬量有限。不過，所有在低溫完成完全矽化鎳的電容結構都還能維持其可靠度，因此，對於未來的低溫化製程的應用而言，完全矽化鎳仍然具有其潛力。

As the dimension of device scaling down, the short channel effects are more severe. Then, in order to control threshold voltage, it is needed to use heavy channel doping. However, the carrier mobility will be reduced and device performance will be degraded, too. For this reason, the single metal gate with suitable work function will be used to control the threshold voltage in the future. However, metal gate got integration difficulties with the self-aligned process. Recently, the FUll SIlicide (FUSI) NiSi gate is investigated as an alternative metal-gate. The nickel silicide gate has several advantages, such as low resistivity, elimination of PDE, tunable work function, and better process compatibility. However, whether the gate oxide reliability is affected by nickel or not is a concern. In this thesis, we have studied the gate oxide reliability with the NiSi gate. The NiSi gate was carried out with different temperature and structures. For the undoped poly-Si and a-Si gate, the amounts of nickel diffusion into the gate oxide increased with temperature, and the oxide was degraded severely after 800oC annealing. For the in situ doped n+ NiSi gate, the gate oxide reliability is still acceptable even with 800oC annealing. The interaction between impurity and nickel is believed a reason of retarded nickel diffusion into gate-oxide. In TEM images of NiSi films, better uniformity and larger grains were observed while with higher RTA temperature. And, from the flat-band voltage shifts, we found the n+ NiSi work function changed with different RTA temperatures. We also used the n+ a-Si/poly-Si and poly-Si/n+ a-Si stacked structures to form NiSi gate, and the gate oxide reliability was affected at high temperature. The interface between a-Si and poly-Si doesn’t seem to affect the nickel diffusion much. Nevertheless, all the samples treated by low temperature annealing sustained the gate oxide reliability well. Thus, FUSI NiSi gate still possesses potential to be used in low temperature process in the future.