完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 何庭緯 | en_US |
dc.contributor.author | Ho, Ting-Wei | en_US |
dc.contributor.author | 王協源 | en_US |
dc.contributor.author | Wang, Shie-Yuan | en_US |
dc.date.accessioned | 2014-12-12T01:33:53Z | - |
dc.date.available | 2014-12-12T01:33:53Z | - |
dc.date.issued | 2008 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT079655519 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/43321 | - |
dc.description.abstract | 近年來,由於半導體的技術極限,提升處理器 (CPU)的運算速度是變的越來越難以達成,因此目前處理器製造商都開始走向多核心的架構來達到提升總體校能的目的,具有多核心處理器的桌上型與筆記型電腦也越來越普及,因而如何有效利用此一架構來增進程式的效能,便是一個相當重要的問題。事件層平行運算 (Event-Level Parallerism) ,簡稱ELP,即是針對多核心架構而設計的網路模擬技術。本篇論文旨在提出一個新的方法來改進ELP的效能。在本篇論文中,我們將會分析ELP的各個重要部份,並根據結果來建立新的ELP架構。最後,我們將這新方法實作到ns-2網路模擬器上,並測量它在不同網路情形下的模擬效能。 | zh_TW |
dc.description.abstract | Multi-core computers have been ubiquitous in the current market. On such a computer, efficiently using the computing power of all cores (CPUs) to finish a task becomes an important and challenging issue. It is difficult for an application (including a network simulator) to automatically gain performance speedups on multi-core systems because the application process can only be run on a single CPU at any given time. To gain performance speedups, an application program needs to be made “multi-threaded” so that its threads can be run on multiple CPUs simultaneously. However, turning an application program to be “multi-threaded” is not trivial and does not necessarily achieve good performance speedups. To solve this problem, an novel “Event-level Parallelism (ELP)” approach was proposed in [7]. In this thesis, we first evaluated the performances of the ELP approach proposed in [7], identified its drawbacks, and proposed a new architecture for the ELP approach. We studied and compared the performances of the original ELP architecture and our proposed new ELP architecture over the ns-2 network simulator. Our results show that our proposed new ELP architecture outperforms the original ELP architecture on simulation speedups in most of the evaluated network conditions. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | ELP | zh_TW |
dc.subject | ns-2 | zh_TW |
dc.subject | 網路模擬器 | zh_TW |
dc.subject | 多核心處理器 | zh_TW |
dc.subject | 多執行緒 | zh_TW |
dc.subject | 平行模擬 | zh_TW |
dc.subject | ELP | en_US |
dc.subject | ns-2 | en_US |
dc.subject | network simulator | en_US |
dc.subject | multi-core | en_US |
dc.subject | multi-thread | en_US |
dc.subject | parallel simulation | en_US |
dc.title | 在ns-2網路模擬器上改進ELP的效能 | zh_TW |
dc.title | Improving the Performance of the ELP Approach over the Ns-2 Network Simulator | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |