以硬體協助之多核心嵌入式系統效能與耗能評估工具

Abstract

有效的效能與耗能評估是嵌入式系統設計時期的關鍵技術。然而，傳統的評估方法難以兼具快速以及精確。此外在多核心逐漸應用於嵌入式系統的今日，傳統的評估方法將面臨更為複雜及困難的挑戰。有鑑於此，本文提出一種以硬體協助且適用於多核心嵌入式系統的效能與耗能評估工具，並予以實現。所提之工具提供程式執行時期硬體事件的監控，並藉此推算出元件耗能，其可避免軟體取樣(Sampling)所造成的額外負擔，以便能呈現系統原始的行為與特性。實驗結果顯示，所提之方法可於100 MHz的四核心仿真環境下進行，精度可達微秒以下，其兼具快速、精細且真實的特性將有助於複雜多核心嵌入式系統設計時期之細部評估與分析。

Effective performance and energy evaluation of embedded systems is one of the critical issues during design phase. However, conventional approaches suffer from difficulties to provide fast and accurate evaluation of the system, especially for those embedded systems using multi-core technology. In this thesis, we propose and realize a hardware-assisted performance and energy evaluation tool for a multi-core embedded system. Our approach provides hardware monitor for runtime programs, and uses these monitor information to estimate the system energy consumption without introducing extra software sampling overhead. The experimental results show that our approach can work at a 100 MHz quad-core emulation platform. The profiling granularity is higher than microsecond. It provides fast and fine-grained evaluation of the multi-core embedded system during the design phase.