具有 LVDS 與 RSDS 低電壓差動訊號傳輸規格之平面顯示器高速輸入輸出緩衝器設計

Abstract

今日平面顯示器持續在提供其色彩濃度與解析度的增加。很多面板製造業者都已經可以量產解析度超過 SVGA (800 × 600 像素) 和 XGA (1024 × 768 像素) 的平面顯示器。隨著平面顯示器解析度的快速增加，位於平面顯示器系統裡直接連接顯示卡到液晶顯示時脈控制器以及液晶顯示時脈控制器到面板驅動電路的介面應該操作於更高的資料傳輸速度。因此，位於平面顯示器系統介面的高速輸入輸出緩衝器設計是有其必要的。本論文共包含三個設計子項，透過三個獨立下線的晶片來驗證這些設計。 第一個設計為採用 0.25-μm 1P5M CMOS 製程技術所實現的一個相位鎖相迴路，其電源電壓為 2.5 V。其所設計的輸出時脈頻率為 200 MHz 而由於使用一個除八的除頻器故輸入參考時脈頻率為 25 MHz。 第二個設計為採用 0.25-μm 1P5M CMOS 製程技術所實現的三個輸入輸出緩衝器，其電源電壓為 3.3 V。這些輸入輸出緩衝器可跟低電壓差動訊號傳輸規格和更小擺幅差動訊號傳輸規格完全相容。此兩種低電壓差動訊號傳輸規格和更小擺幅差動訊號傳輸規格都是用來定義平面顯示器系統裡的介面傳輸。這些輸入輸出緩衝器的資料傳輸速度可以到達每秒 1.2 十億位元 (1.2 Gb/s)，其可以支援解析度為 UXGA (1600 × 1200 像素) 的平面顯示器。 第三個設計為一個可以將 28 位元的大擺幅 (3.3 V) 並列資料轉換成四條低電壓差動訊號傳輸資料流或更小擺幅差動訊號傳輸資料流的傳送器，其採用 0.25-μm 1P5M CMOS 製程技術而其電源電壓為 3.3 V。位於傳送器的相位鎖相迴路擁有七個不同的時脈相位以便將輸入的資料做並列轉串列的轉換。傳送器的資料操作速度可以到達每秒 1.05 十億位元 (1.05 Gb/s)，其可以支援解析度為 SXGA (1280 × 1024像素) 的平面顯示器。

Flat panel displays (FPDs) continue to offer an increase in color depth and resolution, today. Beyond the SVGA (800 × 600 pixels) and XGA (1024 × 768 pixels) resolutions of flat panel displays are ready for production by many flat panel manufacturers. As the resolution of FPDs is increasing rapidly, the interfaces that directly connect a graphics card to a liquid crystal display (LCD) timing controller and a LCD timing controller to flat panel column drivers in FPD systems should be operated at a higher data rate. Therefore, high-speed I/O buffers designed for interfaces in FPD systems are necessary. This thesis includes three topics, which were verified through 3 individual chips. In the first topic, a phase-locked loop (PLL) has been implemented in a 0.25-μm 1P5M CMOS process and the power supply is 2.5 V. The designed output clock frequency is 200 MHz and the input reference clock frequency is 25 MHz due to the divided by eight divider. In the second topic, three I/O buffers have been fabricated in a 0.25-μm 1P5M CMOS process and the power supply is 3.3 V. These I/O buffers are fully compatible with both low-voltage differential signaling (LVDS) standard and reduced-swing differential signaling (RSDS) standard. Both LVDS and RSDS standards are defined for interface transmission in FPD systems. The data rates of these I/O buffers are up to 1.2 Gb/s which can support the UXGA (1600 × 1200 pixels) resolution of flat panel displays. In the third topic, a transmitter which converts 28 bits of full-swing (3.3 V) parallel data into four LVDS or RSDS data streams has been implemented in a 0.25-μm 1P5M CMOS process and the power supply is 3.3 V. The PLL in the transmitter has seven different clock phases in order to perform parallel-to-serial conversion of incoming data. The data rate of the transmitter is up to 1.05 Gb/s which can support the SXGA (1280 × 1024 pixels) resolution of flat panel displays.