高速、低壓差動擺幅之收發器

Abstract

隨著液晶面版的尺寸加大，還有對於顯示器解析度的要求提高，因此單位時間內，顯示卡和液晶顯示器間所需傳輸及接收的資料量也大幅提高，而能達到越高速傳輸的介面電路將為顯示畫面品質高低的關鍵。雖然以往使用並列的方式可達到高速傳輸的目的，但如此一來將會浪費許多導線的成本及可用空間，且使用便利上也受到影響，因此小巧、高速序列傳輸方式成為現在主流。在目前高速傳輸介面電路中，高速、低功率、低雜訊干擾的傳輸條件中又以低電壓差動訊號傳輸 (LVDS)技術被運用的範圍也最廣。 本論文的研究有傳送和接收兩部分，並使用tsmc 0.35um2P4M CMOS製程技術實現，電壓電源為3.3V。傳送器主要利用七相位鎖相迴路和多工器將並列資料轉為序列資料。而量測結果七相位鎖相迴路輸出142.8 MHz的時脈訊號之方均根抖動和峰值抖動分別為11.7 ps和80 ps，而傳送器傳送出1 Gb/s的信號．消耗功率為162mW。 接收器主要是利用三倍取樣的機制來解決資料和時脈時差的問題，利用具有磁滯現象的比較器將由傳送器傳送過來的小信號放大成數位訊號，再利用三組取樣器取樣。接收器每接收到十六筆資料後，做一次取樣相位校正的動作，已確保接收器能接受到最正確的資料。

As the size of the LCD monitor is being enlarged and demands on the resolution, data transmission between display card in computers and a LCD monitor becomes larger and larger. So, the key of high display quality will dramatically depend on the speed of the transmission interface. Although parallel ports can achieve the goal of high speed transmission, it takes more cost and space and, sacrifices convenience. Therefore, the novelty and high-speed serial ports become a maim stream. LVDS-interface techniques are more widely used in the transmission field. It has high speed, low power, low EMI. The thesis is to design a transceiver for LVDS transmission interface. Transceiver is fabricated in 0.35um 2P4M process. Power supply is 3.3V. The transmitter makes use of a 7-phase PLL and a multiplexer to transfer parallel data to serial data. The measured jitters of the PLL output are 11.7 ps (r.m.s.) and 80 ps (peak-to-peak) at 142.8MHz. Transmitter transmits 1 Gb/s serial data normally and total power is 162mW. Receiver uses 3X-sampling skills to overcome time-skew problem. It uses the comparator with hysteresis to amplify incoming small signal to full swing, and then uses three samplers to sample data. The receiver calibrates the sampling phase after receiving sixteen data to make sure the receiver can work correctly.