超越 100Mpixels 之即時JPEG XR影像編碼器設計

Abstract

在現在資訊快速發展的時代，許多手持式裝置與照相機都需要使用到高解析度與高精細度的影像處理，於是對於影像儲存的壓縮率也顯得越來越重要。由Microsoft所開發的最新影像壓縮技術JPEG XR不論在影像壓縮率或是影像的支援度也比傳統的JPEG與JPEG2000都擁有更好的演算法。 在JPEG XR的實踐電路中，有三個最主要的路徑會影響到編碼器的性能。一是適應性的量化器運算(Adaptive Normalization)，二是須不斷更新新的係數掃描順序(Adaptive Scan)，第三個則是判斷最佳的Huffman Tabel並得到最佳的壓縮率。因此，如何設計最佳化的管線設計讓編碼運算進行順暢或是使用並行方式讓編碼器增加輸出量則成為此篇論文最大的挑戰。此篇論文中，我們研究了適應性量化器的特色並利用它對係數數目具有有效減少其數量的能力。進而改善了每個管線中的控制器使其能夠有效的減少多餘的掃描、快速推進每一階的處理器，更有效的減少晶片的耗電與增加編碼器的每個單位時間的輸出量。 經過最佳化的硬體設計後，我們量測了晶片的效能。經量測，四張具有相同大小但擁有不同畫面細節的測試圖片在經過編碼器的處理之後，皆得到近乎相同的運算成果。其運算能力的輸出量達到了超過1 Pixel/Cycle。根據Synposys Design Compiler 0.18 um CMOS合成的結果與設定100MHz的條件之下，晶片的Gate Count為235,377而需使用的SRAMs大小則為992 X 3 channels。編碼器的即時運算能力達到了100Mpixels。

In modern industry, although high resolution and wide dynamic range images had be used with in several applications like digital camera sensors, web display devices, so the compression of visual information becomes more and more important. JPEG XR [1] is an new image coding standard, based on high definition (HD) Photo developed by Microsoft [3]. It supports high compression performance higher than JPEG and JPEG2000. Entropy coding was the throughput bottleneck in previous architectures. There are three feedback loops in entropy coding stage; (1) Control of ModelBits, (2) Updating of the scanning order, and (3) Decision of the Huffman table to be used. Therefore, how to design a pipelined module in a straightforward implementation or processing Macroblocks in parallel structure becomes main design challenge. We generalized the characteristic of Normalization (Update ModelBits) and took advent -age of reduction of Levels. Our propose pipeline controller can optimal the encoding forward steps to decrease un-necessary data processing. We could safely pipeline all the encoding processes including the entropy coding and achieves higher throughput than those of related works. After our optimization, estimation of the encoding speed in our implementation is measured. The four images with same size but different manner are tested and represent quite similar results. The calculated throughput in terms of pixel/cycle shows that our implementation can achieve more than 1 pixel/cycle. The architecture is synthesized by Synposys Design Compiler with 0.18 um CMOS standard cell library. The result shows that the gate count of the designed JPEG XR encoder with 100MHz as target frequency is 235,377, number of used SRAMs is required by 992 × 3 channels. An over 100Mpixels real time JPEG XR encoder is designed.