採多層式方式之消去迴圈演算法建構低密度同位元檢查碼

Abstract

低密度同位檢查碼，其最主要的優點為能夠提供接近通道容量的解碼效率，且適合以平行化的方式來實現，是近年來一直很熱門的研究題目，這些研究當中探討如何提升週長，以增進解碼效率的區塊低密度同位檢查碼，是我們最感興趣的方向，它最主要的概念，是由一個基本矩陣擴展成同位檢查矩陣，而在擴展同時，並消去短迴圈，藉以提升錯誤更正能力，在這篇論文當中，我們提出了多層式的作法，搜尋有最多迴圈的元素，並找出最適合的旋轉移位量，來進行擴展和消去迴圈的動作，實驗數據顯示，多層式消去迴圈的方法，能以很低的擴展倍數，就消去所有的短迴圈，也因為如此，在硬體實現時，可藉由多個模組來增加平行化，並保有區塊低密度同位檢查碼的解碼效能。

The main advantage of Low-Density Parity-Check codes is that they provide near-channel capacity decoding efficiency and are suitable for parallel approach implementation. We are most interested in the research topic which aims to enhance decoding efficiency in codes with large girth. The most important concept is to enhance error correction capability by eliminating short cycles in a parity-check matrix expanded from a small base matrix. In this thesis, we propose a hierarchical elimination algorithm to expand and break short cycles by searching for an element that contains the largest number of short cycles and identifying the proper cyclically shifted values. According to our experimental data the hierarchical elimination method can eliminate short cycles with a very low expanding value. In addition, the hardware parallelism can be increased with multiple modules and the Block-LDPC codes efficiency can still be retained.