利用動態基體偏壓與電源閘技術之低功率設計

Abstract

本論文使用動態基體偏壓與電源閘技術來實現低功率之電路設計。基於系統晶片之使用彈性與重複使用特性，一個可產生多種輸出電壓的基體電壓產生器被提出且用TSMC 100nm CMOS技術設計。此電路可經由改變輸入信號設定來得到不同的輸出電壓。另外，一個可產生雙電壓的基體電壓產生器被用在靜態隨機存取記憶體陣列的設計，藉此觀察基體偏壓對於漏電流抑制的有效性。電路模擬和佈局是用TSMC 0.13um CMOS技術實現。模擬結果顯示64字元的記憶體單元減少75%的淨功率消耗，32字元則是64%。 一個利用行解碼器與列解碼器來控制電源閘的靜態隨機存取記憶體陣列被提出，且利用TSMC 0.13um CMOS技術來實現電路設計與佈局。同一條字線上的字元被分成數個區塊，每一個區塊擁有各自的電源閘控制元件。模擬結果顯示可以減少大量的靜態和動態的功率消耗，而且功率-延遲乘積說明對於速度變慢的影響極小。使用8字元的區塊，佈局面積將增加20.7%，而使用16字元區塊會增加12.1%的面積。若使用32字元區塊，則面積增加8.1%。此技術可以應用在靜態隨機存取記憶體，暫存器，內容定址記憶體，動態隨機存取記憶體，快閃記憶體，快取記憶體，或是其他類似之記憶體與邏輯電路。

The low-power circuit designs using dynamic body-biasing and power-gating techniques are realized in this thesis. For the flexibility and reusability in System-on-Chip designs, an on-chip configurable body-bias generator that produces various voltage levels is proposed and simulated in TSMC 100nm technology. The output voltage can be controlled through digital input signals. A dual-level on-chip body-bias generator is presented and combined with SRAM cell arrays to observe the effectiveness in leakage suppression. Simulation results in TSMC 0.13um technology show that 75% and 64% net cell leakage reductions are achieved for 64-bit and 32-bit wordlines, respectively. The physical layout is implemented in TSMC 0.13um technology and triple-well structure is necessary for separating body nodes of transistors. A column/row co-controlled SRAM cell arrays scheme is also proposed and simulations and layout are implemented in TSMC 0.13um technology. The cells on the same wordline are divided into blocks and each block has a dedicated gating device. The gating devices are controlled by signals from both column and row decoders. Simulation results show a great amount of active and standby power saving and power-delay product demonstrates that the induced performance overhead is insignificant. Moreover, the area overheads for 8-bit block and 16-bit block conditions are 20.7% and 12.1%, respectively, and only 8.1% is for 32-bit block condition. This technique can be applied to SRAM, register file, CAM, DRAM, flash memory, cache, or other similar memory and logic circuits.