探討碳離子佈植與退火溫度對源汲極接面深度之影響

Abstract

硼離子因暫態增益擴散現象造成的短通道效應，使其在元件尺寸微縮時應用在P型金屬氧化物半導體源/汲摻雜質時受到限制。本論文研究目的在於利用碳離子在硼離子佈植之前植入，運用碳離子捕捉間隙式缺陷的特性，來抑制硼的擴散情形。在實驗設計上將碳離子採用不同條件植入與退火，再以二次離子質譜儀和展阻分析儀來獲得各組碳與硼的緃深分佈，以其緃深結果得知碳離子佈植在抑制硼擴散上的最佳化設定。再利用電性分析取得一些元件重要數據如：臨界電壓、有效通道長度、飽和電流、源/汲極與閘極間的寄生電容、薄片電阻、臨界電壓的下降效應、汲極電流與閘極電壓對應圖，以用來評估在最佳化設定下植入的碳離子對元件所產生的正負影響。

Boron's utilization as PMOS source/drain dopant resource is restricted by it's transient enhanced diffusion phenomenon that introduce short channel effect when scaling device size. The main purpose of this thesis is to implant carbon ions prior to boron ion implantation, as a result of the carbon's characteristic which can capture interstitial defects to suppress boron diffusion. In this experiment will be designed using different conditions of carbon ion implantation and annealing, and then to obtain carbon and boron carrier profiles by secondary ion mass spectrometry and spreading resistance probe. With their profiles show the optimal setting of carbon ion implantation to suppress boron diffusion. After that, we obtain some critical device electrical data such as：threshold voltage, effective channel length, saturation current, source/drain to gate overlap capacitance, sheet resistance, threshold voltage roll-off effect, and Id-Vg curve to evaluate the positive and negative impacts to device performance when carbon is implanted as optimal setting.