錫鉛覆晶銲錫中金屬墊層電遷移與熱遷移行為之研究

Abstract

電子構裝技術是指從半導體積體電路製作完成後，與其它的電子元件共同組裝於一個連線結構(Interconnection)之中，以達成特定設計功能的所有製程。然而隨著元件的輕、薄、短、小，以及功能與效用的追求，晶片內部I/O接點的數目與日俱增，因此Flip Chip使用覆晶銲錫矩陣式排列的 I/O為最有效的解決方式。然而因為製程的演進使得銲錫尺寸持續微縮， 晶片運作時通過銲錫的電流密度與日俱增。因此有關銲錫本身可靠度議題也越來越重要。 在本文中我們將研究晶片運作時銲錫內部的電遷移與熱遷移對可靠度造成的影響。我們使用凱文結構的方式來量測與監控銲錫球接點的電阻變化，並且定義銲錫接點電阻上升 20% 、100%、500%與完全斷路四種實驗條件來測試電遷移的影響，再搭配IR上銲錫通電時內部的溫度梯度來估算熱遷移的影響，最後再透過光學顯微鏡與電子顯微鏡研究不同通電時期電遷移與熱遷移的混合機制。 我們發現當試片在分別 150℃、160℃ 加熱盤上同時加以0.8安培電流時，各種原子的作用力方向不同會影響破壞時間的長短與介金屬化合物生成的多寡。其中當原子電遷移作用力與熱遷移作用力的方向是同向時，破壞的機制會更快速；而電遷移與熱遷移的方向是反向時，破壞的機制會減緩。

Electronic Packaging Technology is a process to fabricate all of the electronic devices in one interconnection structure. As the consumer electronic products move toward more lightly, thinner and smaller, we need higher density of input/output joints. Therefore, Flip Chip Technology is a best solution. Along with the solder bump shrinking and current density increased. Reliability issue is more and more important. In the study, we investigate the behavior of Electromigration and Thermomigration by using Kelvin Structure to measure the resistance of solder bump. We define the experiment condition as the resistance increased 20%、100%、500% and opening stage. We also evaluate the thermal gradient of bump cross-section from IR’s snapshot. Finally, we can use the OM and SEM to look into the mix mechanism of Electromigration and Thermomigration. When the current stress were applied on a hotplate with temperature at 150℃、160℃ and the current is 0.8 ampere at the same time. The difference of atomic migration force direction will influence the failure time and Intermetallic compound (IMC) growth. If Electromigration and Thermomigration force are in the favorable direction, it will speed the failure mechanism. If Electromigration and Thermomigration force are unfavorable direction, it will slow down the failure mechanism.