標題: 多晶矽奈米線結合內嵌式奈米矽晶體之SONOS記憶體元件之研究
A Study on Poly-Si Nanowire SONOS Devices with In-Situ Embedded Silicon Nanocrystals
作者: 羅正瑋
Luo, Cheng-Wei
林鴻志
黃調元
Lin, Horng-Chih
Huang, Tiao-Yuan
電子研究所
關鍵字: 內嵌式奈米矽晶體;SONOS
公開日期: 2009
摘要: 在本篇論文中,我們利用本實驗室最近發展出的多晶矽奈米線製程來製作SONOS元件,此製程無須使用先進且昂貴的設備,其製作流程簡單且極富彈性。藉由稍微調整製程的參數,我們製作了四種不同截面尺寸的奈米線元件。相較於平面結構元件,奈米線元件具有較好的次臨界擺幅(subthreshold swing)以及較大的開關電流比(on/off current ratio),而且奈米線元件在寫入和抹除速度上也有很大幅度的改善。在這四種不同截面尺寸的奈米線元件中,我們的數據顯示較細的元件擁有較快的寫入和抹除速度,但也會較快進入寫入飽和狀態。 此外,我們運用內嵌式奈米矽晶體(silicon nanocrystals)製程,將奈米矽晶體嵌入氮化矽層間,以此來製作SONOS元件。利用改變奈米矽晶體在氮化矽層內的相對位置,可以得到許多特性非常不同的元件。當奈米矽晶體位於氮化矽及穿隧氧化層間時,元件會有最快的寫入和抹除速度。而當奈米矽晶體位鑲嵌於氮化矽內時,元件的電荷保持能力(retention)最好。 本論文中的所有元件,在可靠度方面都擁有不錯的電荷保持能力及忍耐力(endurance),這些元件都可以承受超過一萬次的重複寫入及抹除,並且在十年儲存後,仍可維持大於0.5 V的記憶窗(memory window)。
In this thesis, we employed a simple, low cost, and flexible way that was recently developed by our group to fabricate NW devices. With a slight modification in fabrication procedure, gate-all-around NW SONOS devices with four different cross-sectional dimensions were implemented. Compared with planar control, NW devices possess higher on/off current ratio and superior SS. Moreover, NW SONOS devices have apparent improvement on P/E speed. In these four SONOS splits with different dimensions, the thinnest exhibits the best SS due to its best gate controllability. Comparing the P/E characteristics, thinner device depicts higher P/E speed but reaches the programming saturation more quickly. We have also fabricated Si NCs devices based on the poly-Si NW SONOS technology. Accompanying with the changing of Si NCs location in the nitride trapping layer, these memory devices also exhibit very different P/E performances. Specifically, when Si NCs are located at the interface of tunneling oxide and nitride layer, the device possesses the fastest P/E speed among all splits. On the other hand, when Si NCs are embedded in the nitride layer, the device shows the best retention performance. For reliability test, all NW SONOS devices studied in this thesis can maintain acceptable memory window after 104 P/E cycles. The data retention measurements of these devices show that the memory window can be larger than 0.5 V after 10 years at room temperature.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711505
http://hdl.handle.net/11536/44204
顯示於類別:畢業論文


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