標題: | Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices |
作者: | Luo, Cheng-Wei Lin, Horng-Chih Lee, Ko-Hui Chen, Wei-Chen Hsu, Hsing-Hui Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Gate-all-around (GAA);nanocrystal (NC);nanowire (NW);poly-Si;silicon-oxide-nitride-oxide-silicon (SONOS) |
公開日期: | 1-七月-2011 |
摘要: | Trap-layer-engineered poly-Si nanowire silicon-oxide-nitride-oxide-silicon (SONOS) devices with a gate-all-around (GAA) configuration were fabricated and characterized. For the first time, a clever method has been developed to flexibly incorporate Si-nanocrystal (NC) dots in different locations in the nitride layer. Three types of poly-Si GAA SONOS devices with Si-NC dots embedded in the block oxide/nitride interface, the middle of the nitride, and the nitride/tunnel oxide interface, respectively, by in situ deposition were fabricated and investigated in this paper. Our results indicate that the optimal NC location appears to be somewhere between the middle and bottom interfaces of the nitride layer. |
URI: | http://dx.doi.org/10.1109/TED.2011.2140321 http://hdl.handle.net/11536/22033 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2011.2140321 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 58 |
Issue: | 7 |
起始頁: | 1879 |
結束頁: | 1885 |
顯示於類別: | 期刊論文 |