研究鍺表面鈍化於未來鍺通道金氧半場效電晶體之效能影響

Abstract

此論文中，首先我們分析二氧化鍺表面鈍化的鍺電容。透過電導和費米能階移動效率的方法說明能帶缺陷密度可因300度的氫氣氮氣混合之熱退火而被有效降低，而在能隙中央位置的值大約在5×1011cm-2eV-1左右。透過ln⁡τ對ET-Ei圖型的外插，我們可萃取出缺陷的電子或電洞補捉截面積，分別是2.7-4.2×10-16cm2和7.8-9.6×10-16 cm2。並透過低溫量測萃取出鍺能隙中的缺陷分佈。 根據電容的經驗，我們成功地製作出搭配原子層沉積三氧化二鋁高介電層之反轉式(inversion-mode)純鍺P型場效電晶體。表面鈍化與無表面鈍化的樣品其載子遷移率分別為矽普遍曲線(universal curve)之1.7倍與1.3倍。而由於300度的氫氣氮氣混合之熱退火可有效降低缺陷密度，使我們得到較佳的電流開關比(3.3 orders)與次臨界擺幅(170mv/dec)。透過電荷幫浦(charge pumping)量測，估計出能隙中央位置的平均缺陷密度與電子和電洞補捉截面積的幾何平均，並與分析電容所萃取出來的結果一致。利用我們的實驗結果分析在鍺表面加入二氧化鍺的優缺點。好處是可得到較低的缺陷密度與較高的載子遷移率;缺點是可靠度表現較差，有較嚴重的載子捕捉現象與次臨界擺幅劣化現象。 最後，我們製作出搭配原子層沉積三氧化二鋁高介電層之反轉式(inversion-mode)純鍺N型場效電晶體。我們先用實驗證明SiO2/GeO2絕緣比SiO2絕緣有更低的接面逆偏漏電，而同樣是SiO2/GeO2絕緣700度比500度退火有更低的接面逆偏漏電。元件的電流開關比可到達三個數量級(W/L=100μm/10μm)，不過卻有很大的源極與汲極寄生電阻。N型場效電晶體比起P型場效電晶體有較差的電性表現，將可能原因整理出來分別是:在介面處帶有大量負電(受體形式介面缺陷)造而嚴重的庫倫散射、反轉層電荷流失、與很大的寄生電阻。

In this thesis, firstly, high-k/GeO2/Ge capacitors were fabricated and analyzed electrically. Interface state density was shown to be reduced effectively through 300°C 30 minutes FGA, with value about 5×1011 cm-2eV-1 near the midgap from either conductance or Fermi-level efficiency method. By extrapolation of ln⁡τ vs (E_T-E_i) plot, σ_n and σ_p were 2.7-4.2×10-16cm2 and 7.8-9.6×10-16 cm2 respectively. Besides, Dit distribution in the bandgap was extracted by means of low temperature measurement. Secondly, from the experiences in high-k/GeO2/Ge capacitors, we successively demonstrated the device characteristics of the inversion-mode Ge p-FETs with ALD-Al2O3 gate dielectrics. GeO2 passivation as well as no passivation sample had their high field mobility 1.7X and 1.3X higher than the Si universal curve respectively. Also, better on/off ratio (3.3 orders) and subthreshold swing (170mv/dec) were attained for Ge p-FET after 300°C 30 minutes FGA, resulted from lower reverse bias junction leakage and better interface quality. Then, charge pumping was applied to reconfirm the results in Chapter two. (D_it ) ̅ after FGA between E_(em,e) and E_(em,h) is 4.2×1011cm-2eV-1 and √(σ_p σ_n ) was 5.4×10-16 cm2 for 500°C GeO2 passivation sample. Furthermore, pros and cons of adding the GeO2 layer were summarized: lower Dit value verified from either charge pumping or gated diode measurement made the mobility higher for GeO2 passivation sample, while it suffered from more carrier-trapping due to border traps at the GeO2/Al2O3 interface and more severe subthreshold swing degradation. Finally, device characteristics of inversion-mode Ge n-FETs with ALD-Al2O3 gate dielectrics were also demonstrated. SiO2/GeO2 isolation as well as 700°C 30s dopant activation did we obtain the lowest reverse bias junction leakage of 1.9×10-2 A/cm2 at 2V and magnitudes of the rectifying ratios reached 4.2 orders. On/off ratio of our n-FETs (W/L= 100μm/10μm) reached 3 orders but series resistance larger than 1.7kΩ was extracted. It was concluded that much severe n-FET performance degradation compared with p-FET could be explained in terms of fast trapping at Ge/GeO2 interface, slow trapping by GeO2/Al2O3 border traps and parasitic S/D series resistance.