閘極高介電值絕緣層穿隧電流的模擬

Abstract

因為高介電值絕緣層可以達到抑制閘極漏電流的目的，所以傳統的閘極氧化介電層正逐漸被高介電值絕緣層所取代。雖然高介電值絕緣層的電性特性已經被發表過了，但是高介電值絕緣層的物理基礎模型還沒有被完全的研究透徹。 在此論文中，建立一個針對n型金氧半電晶體的高介電值絕緣層電子穿隧模型。針對高介電值絕緣層穿隧電流的機制將會逐步地一一介紹。首先我們用複矽晶閘極單氧化層的簡易結構來解釋其操作原理。這個原理包含四個關鍵的參數:反轉層的電荷密度，電子對於氧化層/矽介面的撞擊頻率，WKB的傳輸機率，以及反射波的修正因子。 接著，將只有一層的閘極絕緣層模型擴展到適用於高介電值絕緣層的二層結構。對於電子穿隧模型變數的影響將會詳細地分析。並且在對於高介電值絕緣層穿隧電流的模擬及量測上得到卓越的符合。重要的是，穿隧變數以及能帶圖能夠相應的得到，這可以更加地了解電子在高介電值絕緣層中的閘極穿隧機制。

Because the high-K stacks could achieve the target in suppressing the gate leakage current, conventional SiO2 gate dielectrics is being gradually replaced by high-K materials. Although electrical characteristics have been demonstrated for high-K stacks, a physically based model of tunneling currents through high-K stacks has not been thoroughly investigated. In this thesis, an electron tunneling model of high-K stacks will be constructed for nMOSFETs. The mechanisms responsible for the tunneling current will be introduced step by step. First, we explain the operational principle in a simplified framework of one oxide layer with poly gate. This principle comprises four key physical parameters: the inversion layer charge density, the electron impact frequency on SiO2/Si interface, the WKB transmission probability, and the reflection correction factor. Then, the structure to treat the case of only one gate dielectric layer model is augmented to that of a two-layer high-K stacks. The impact of the model parameters on the electron tunneling is analyzed in detail. Excellent agreements between simulated and measured tunneling currents are achieved. Importantly, the tunneling parameters and energy band diagrams are obtained accordingly, leading to a better understanding of the tunneling mechanism of electrons in high-K gate stacks.