應變矽CMOS元件中隨機摻雜與隨機界面缺陷引起的臨界電壓變異度研究

Abstract

90奈米及以下的CMOS技術，採用應變矽技術得以延續摩耳定律(Moore’s Law)，以提昇元件性能。近年的研究中顯示在n型MOSFET元件，SiC在S/D的結構提供了高的驅動電流。而在p型MOSFET元件中，單軸的應變結構SiGe在S/D及嵌入式擴散阻擋層(EDB)，有著良好的可靠度和效能。然而隨著CMOS元件微縮到奈米尺度，對於前瞻CMOS技術而言，如何降低臨界電壓變異度(Vth variation)成為一項重要的議題。而隨機摻雜擾動(Random Dopant Fluctuation, RDF)被認為是臨界電壓變異度的主要原因。此外，由製程技術所產生的隨機界面缺陷擾動(Random Interface Trap Fluctuation, RTF)亦會增加臨界電壓變異度。

本論文中，我們利用可將由隨機摻雜擾動引致臨界電壓變異度正則化(Normalization)的Takeuchi plot來分析應變矽元件的變異度。首先，我們解釋了應變矽元件可改善臨界電壓變異度的原因，並藉由溫度、汲極電壓和基板電壓等效應來驗證應變矽元件擁有較佳的變異度。此外，stress之後所造成的隨機界面缺陷導致臨界電壓變異度的增加亦可利用Takeuchi plot來分析。實驗結果顯示，退化的BVT與界面缺陷的數目呈比例關係。然而，在應變矽n型MOSFET元件中，由於反轉層電子與界面缺陷的距離較近，使得庫倫散射(Coulomb scattering)變得較強導致臨界電壓變異度退化的較嚴重。對應變矽p型MOSFET元件而言，退化的臨界電壓變異度即與應變效應無關。

For the CMOS device technology with gate length 90 nm and beyond, strained technique has been a successful technology to extend the Moore’s law with further device scaling. Recent studies have revealed that the most mature CMOS technology is by the use of different strain techniques for n-MOSFET and p-MOSFET respectively. The use of SiC in the source and drain structure shows high driving current ability for n-MOSFET device. For p-MOSFET device, uniaxial structure with SiGe on source and drain with EDB (embedded diffusion barrier) seems to be promising in terms of its performance and reliability. However, as CMOS devices are scaled to the nanoscale dimension, reducing Vth variation becomes a significant issue for advanced CMOS technology. Random dopant fluctuation (RDF) is the major source of Vth variation in scaled bulk CMOS. Furthermore, stress-induced random traps fluctuation (RTF) is also considered to be another source of the enhanced Vth variation after the hot carrier stress.

In this thesis, the variability of strained devices has been reported. The random dopant fluctuation induced Vth variation can be normalized by Takeuchi plot. First, the reasons for Vth variation improvement of strained devices are analyzed. The factors affecting the Vth variation which include temperature, drain bias, and substrate bias are examined. Experimental results show better variability of strained devices. Secondly, the basis of the enhanced Vth variation caused by stress-induced random traps can still follow the Takeuchi plot. The results show that the aggravated BVT is proportional to the number of interface traps. However, for strained n-MOSFETs, due to the closer distance between inversion layer electrons and interface traps, Coulomb scattering limited by interface traps becomes strongly enhanced which results in a faster aggravation of Vth variation. For strained p-MOSFETs, the aggravated Vth variation is unrelated to the strain effect.