積體電路元件充電模式之靜電放電防護設計

Abstract

在奈米CMOS製程裡，積體電路的電晶體必須使用很薄的閘極氧化層去達成高速並且低耗電的效能。但是靜電放電(electrostatic discharge, ESD)的問題不會隨著奈米CMOS元件變小而減弱，所以在奈米CMOS製程下的靜電放電防護設計是更加艱難的。在人體放電模式(human-body model, HBM)、機器放電模式(machine model, MM)、和元件充電模式(charged-device model, CDM)三種靜電放電的測試標準裡，元件充電模式靜電放電對積體電路的衝擊更為嚴重。元件充 電模式之靜電放電是由於積體電路產品因磨擦、移動、或其他因素而在晶片內部累積了靜電電荷，當某個接腳瞬間接地，靜電電荷便會經由此接腳自晶片內部流出來。由於系統單晶片的發展趨勢下，晶片尺寸越來越大，而累積在晶片的靜電電荷也越來越多，在使得積體電路更容易遭受元件充電模式之靜電放電破壞。 在本論文裡，第一部份的研究主題探討當一個輸入端的接腳接地而發生元件充電模式的靜電放電事件時，經由電感耦合(inductive coupling)的方式而造成內部電路的電晶體損壞。第二部份的研究主題是針對積體電路內部的電晶體在不同的防護設計條件之下，檢驗其對元件充電模式靜電放電之耐受能力。 本論文之兩項研究主題皆已於65奈米CMOS製程中驗證，實驗結果可供日後之元件充電模式之靜電放電防護設計作參考。

With the nanoscale of CMOS processes, the devices in the integrated circuits (ICs) have been fabricated with very thin gate oxide to achieve high-speed and low- power consumption. But, electrostatic discharge (ESD) events were not scaled down with nanoscale CMOS technology. Thus, it becomes a challenging task of ESD protection design in nanoscale CMOS processes. Among the three component-level ESD test standards, therefore are human-body model (HBM), machine model (MM), and charged-device model (CDM), CDM event becomes very critical because of the very thin gate oxide in nanoscale CMOS transistors and the larger die size for the application of system on chip (SoC). The very thin gate oxide causes a very low gate oxide breakdown voltage, which the MOS transistor become more vulnerable to ESD. More static charges can store in the larger die size in an IC of SoC application, which lead to larger discharging current during CDM ESD event. CDM ESD current has features of short duration of few nano-seconds and huge peak current of several. Therefore, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to IC designers. Some ESD protection designs against CDM ESD events have been presented to protect the input/output (I/O) buffers which connect to the external pins. Besides the I/O buffers, the core circuits also suffered the dangers as the CDM events happened at the I/O buffers and coupled to core circuits. In this work, the CDM ESD robustness of core circuits with coupling effects was investigated in a 65-nm CMOS process. Besides, the protection design for internal MOS transistor is also important during the CDM event. In this thesis, the CDM ESD protection devices with different layout conditions have also been investigated in a 65-nm CMOS process. The experimental results in this thesis can be the reference for the CDM ESD protection design.