新型PHINES和PREM快閃記憶體及氮化矽型發光電晶體之研究

Abstract

摘要

在本論文中，我們研究兩種新型非揮發性快閃記憶體架構︰PHINES (Programming by hot Hole Injection Nitride Electron Storage)和PREM (Programmable Resistor with Erase-less Memory)。另外我們也研究一種新式的氮化矽型發光電晶體 (Silicon-Nitride based Light Emitting Transistor︰SiNLET)。我們將介紹並討論這些元件的結構、操作原則及元件特性。 在第二章中，我們架構了一種新型的PHINES記憶胞。PHINES是使用氮化矽缺陷捕捉儲存的元件結構。抹除(Erase)是利用Fowler-Nordheim電子注入提昇臨界電壓(threshold voltage)的方式，程式化(Program)是利用帶對帶穿遂產生之熱電洞注入以降低局部臨界電壓的方式。PHINES可達成一個記憶胞儲存二位元、低功率抹除與程式化、高的寫入抹除次數(Endurance)及好的資料保持力(Retention)。以外，PHINES記憶胞可以被編排在NOR型和NAND型陣列中，並可同時使用於編碼快閃記憶體(Code flash memory)和資料存取快閃記憶體(Data flash memory)的應用。在第三章中，我們引進一種新型的帶對帶穿遂電流讀取方式(BTB sensing scheme)和一種改良的NAND型陣列。PHINES記憶胞使用帶對帶穿遂電流讀取方式後，將可以排除二位元間的相互干擾(2-bit interaction)，並且在二位元操作時，得到非常大的操作空間和非常好的元件特性。在第四章中，我們將討論PHINES記憶胞在微縮時的挑戰。PHINES記憶胞顯示出非常好的微縮能力。在NAND型陣列架構下，一位元與二位元儲存的PHINES記憶胞分別可以微縮到十五奈米和三十奈米世代。 在第五章中，我們發表了一種應用於系統單晶片的新型PREM快閃記憶胞。PREM結合了一種新式 “無抹除”的操作法和超薄氧化矽中漸進式崩潰的特性。在CMOS標準製程中，其製程完全不需額外的光罩或只需一道額外的光罩。PREM記憶胞具有多次寫入(Multi-time programming)、多值記憶(Multi-level cell)、非揮發性、和低壓操作的特性，並且具有很好的可靠度。 在第六章中，我們研發了一種新式的氮化矽型發光電晶體。此三端電致發光元件是使用SONOS型元件結構，而且製程與CMOS元件製程相容。光子的產生是介由Fowler-Nordheim電子注入、帶對帶穿遂產生之熱電洞注入、及載子經由氮化矽缺陷捕捉與再結合等機制綜合所造成。氮化矽型發光電晶體的元件等效面積只有0.616□m2，適合於顯示器與光通訊等的應用。

Abstract

In this dissertation, we investigate two novel non-volatile flash memory architectures named PHINES (Programming by hot Hole Injection Nitride Electron Storage) and PREM (Programmable Resistor with Erase-less Memory). We also study a novel Silicon-Nitride Based Light Emitting Transistor (SiNLET). The cell structures, operation principles, and device performances are introduced and discussed. In chapter 2, we construct a novel PHINES memory cell. PHINES uses a nitride trapping storage cell structure. Fowler-Nordheim injection is performed to raise Vt in erase while programming is done by lowering a local Vt through band-to-band tunneling induced hot-hole injection. Two-bits-per-cell feasibility, low power program/erase, good endurance, and good data retention are demonstrated. PHINES cells can be arranged in NOR-type and NAND-type array for both code and data flash applications. In chapter 3, a novel BTB sensing scheme and a modified NAND-type array are introduced. PHINES cell with BTB sensing scheme can eliminate the issue of 2-bit interaction, and a large operation can be obtained in 2-bits-per-cell operation. In chapter 4, the scaling challenges of PHINES cell are discussed. PHINES memory cell shows high scalability, and 15nm generation for 1-bit-per-cell storage and 30nm generation for 2-bit-per-cell storage are feasible in NAND-type array architecture. In chapter 5, a novel non-volatile memory cell named PREM is proposed for SOC applications. PREM combines a novel “erase-less” algorithm and the progressive breakdown of ultra-thin oxide. No extra mask is needed with CMOS standard process. MTP (multi-time programming), MLC (multi-level cell), non-volatility, and low voltage operation are realized. Good reliability is demonstrated. In chapter 6, a novel silicon-nitride based light-emitting transistor (SiNLET) is investigated. This three-terminal electroluminescence device uses a SONOS-type structure, and its process is compatible to standard CMOS devices. Photons are generated by Fowler-Nordheim electron tunnel-injection, band-to-band tunneling induced hot-hole injection, and carrier trapping/recombination via nitride traps. SiNLET with an effective device area of 0.616 □m2 is demonstrated for display and optical communication purposes.