具有高介電係數閘極介電層之薄膜電晶體製作及特性研究

Abstract

在本論文中提出整合高介電係數閘極介電層製程，來改善低溫複晶矽薄膜電晶體以及有機五環素薄膜電晶體的特性。首先提出具有高介電係數氧化鐠閘極介電層的低溫固相再結晶複晶矽薄膜電晶體，並且在施行固相再結晶退火前，對非晶化矽薄膜進行氮離子植入。結果顯示，在一定濃度的氮離子植入非晶化矽情況下，能夠在固相再結晶的退火過程中，修補晶粒邊界的缺陷態位，進而大幅改善低溫複晶矽薄膜電晶體元件的電性，而且此氮離子修補技術亦可在低溫複晶矽薄膜裡形成較強的矽-氮鍵結，來取代一般較弱的矽-矽鍵結和矽-氫鍵結，來增進元件對熱載子效應的免疫力。另一方面，使用具有高介電係數的氧化鐠閘極介電層，能夠在相同的等效氧化層厚度下，得到較大的閘極電容密度，加強電晶體閘極的控制能力，使複晶矽通道區產生更多的少數載子，迅速填滿補晶粒邊界的缺陷態位，以致於能大幅地改善薄膜電晶體的臨界電壓、次臨界斜率等電性。第二部分，對於有機五環素薄膜電晶體，我們也整合具有高介電係數的氧化鑭釔閘極介電層，預期得到良好的電性結果。結果顯示，高介電係數的氧化鑭釔的閘極介電層，具有高的閘極電容密度和低的閘極漏電流，能夠讓有機薄膜電晶體的五環素通道，在飽和累積工作區間的操作下，成功誘導產生更多的累積載子，來大幅降低有機薄膜電晶體的操作電壓至兩伏特內。因此，整合高介電係數閘極介電層的薄膜電晶體，將會符合往後顯示器科技的發展趨勢，適合在高速元件或低電壓操作電路的應用。

In this thesis, we integrate high dielectric constant (high-κ) materials as gate dielectrics to improve the electrical performances of the low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) and the pentacene-based organic TFT (OTFT). First, we study the LTPS TFT with a high-κ praseodymium oxide (Pr2O3) gate dielectric and incorporating with nitrogen implantation before solid-phase crystallization (SPC) annealing. Nitrogen atoms with appropriate dosages of 5x1012 cm-2 implanted into amorphous silicon (a-Si) film could passivate the trap states in grain and in grain boundaries during SPC annealing and greatly improve electrical performances. This nitrogen modification could form the strong Si-N bonds in place of the weak Si-Si and Si-H bonds to enhance the immunity against hot-carrier stress. Besides, using Pr2O3 as a gate insulator could obtain a thin equivalent-oxide thickness (EOT) of 8 nm and a high gate capacitance density of 432 nF/cm2 with well gate controllability, compared to conventional tetraethoxylsilane (TEOS) oxide. Because the poly-Si channel could induce more minority carriers to quickly fill up trap states in grain boundaries, the threshold voltage and the subthreshold swing of the LTPS TFT could be greatly improved by integrating high-k gate dielectrics. Second, we also demonstrated the pentacene-based OTFT with a high-κ lanthanum-yttrium oxide (LaYOX) gate dielectric to achieve high-performance characteristics. The results show that the 30-nm LaYOX film as the gate insulator of the OTFT device exhibits a high capacitance density of approximately 410 nF/cm2 and a low leakage current below 20 nA/cm2 biased at -4 V. It could induce more accumulated charges in the pentacene channel layer to obtain good device performances, such as a low threshold voltage of 1.25 V, a low subthreshold swing of 265 mV/Dec., and a field-effect mobility of 0.22 cm2/V-s, under the 2-V low-voltage operation. Therefore, these TFT devices with high-k gate dielectrics integration are suitable for high-speed or low-voltage electronic applications in flat panel display (FDP) field in the near future.