鈣鈦礦結構薄膜應用於半導體記憶體之特性研究

Abstract

本論文主要為探討鈣鈦礦結構薄膜應用於半導體記憶體之特性。於單電晶體鐵電記憶體(1T FeRAM)研究上由原本的金屬/鐵電層/半導體(MFS)結構演進到金屬/鐵電層/絕緣層/半導體(MFIS)結構和金屬/鐵電層/金屬/絕緣層/半導體(MFMIS)結構，絕緣層具有作為與半導體間的緩衝層及降低元件操作電壓的功能外，必須同時具備低漏電流的特性以增加元件的記憶時間，所以絕緣層必須具有高介電常數與低漏電流特性，此部份與高介電閘極氧化層的要求是相同的。另一方面為鈣鈦礦結構薄膜具有電阻轉換特性，可以做非揮發性記憶體的應用。第一章主要在回顧對於高介電閘極氧化層的需求由來，並討論對於目前高介電閘極氧化層所遇到的問題，並對於其特性之要求。另一方面對於電阻式非揮發性記憶體作基本介紹，包括其目前研究的材料、製程與電路架構、轉態原理和對元件之特性要求均作詳盡的解說。第二章對實驗流程作詳細說明，及所需要的物性與電性量測之原理。

第三章則是利用氮化處理與特殊的熱製程方式來降低高介電閘極氧化層之界面層厚度與界面缺陷密度。氮化處理可以降低氧化矽的成長以減少界面層厚度並阻止閘極材料擴散進入矽基板，可以同時降低等效氧化層厚度和於反轉區偏壓時的電流值。利用特殊的熱製程方式則可以降低界面的缺陷密度而使得漏電流降低。

第四章為分別於氧氣氛與氮氣氛下成長鈦酸鍶薄膜，可以發現於氮氣氛下成長之薄膜具有較小的等效氧化層厚度與較大的漏電流，這是由於氮元素可以抑制與矽基板接觸之間界面層的成長而達到較小的等效氧化層厚度，但是於氮氣氛中成長時則會因為薄膜中氧空缺較多而使得漏電流變大。在漏電流較大的元件中可以發現其電流於反轉區會隨著電壓增加而趨於飽和，而電容亦在反轉區內有深空乏的現象，將此兩種現象關聯可以發現由於載子的數量不足以供應電流，所以空乏層隨著電壓增加而變寬，同時由於載子的數量不足導致電流隨著電壓增加而趨於飽和，利用此關聯性，可以萃取出矽基板的少數載子生存期，此方法可以用來監控基板於製程過後的缺陷數量。

第五章為利用交流磁控濺鍍法來成長鉻摻雜的鋯酸鍶薄膜，此薄膜具有可重複操作的電阻改變特性可以作為非揮發性記憶體之應用。其高電流狀態遵守ohmic conduction的電流機制，而低電流狀態遵守Frenkel-Poole emission的電流機制。其兩電流狀態之電阻值差距達五個數量級，為目前鋯酸鍶薄膜中之最大值。其轉態時間由低電流狀態轉至高電流狀態僅需5奈秒，而由高電流狀態轉至低電流狀態卻需要500微秒，其差距達5個數量級。

第六章為利用交流磁控濺鍍法來成長不同優選方向的鋯酸鍶薄膜，並研究不同優選方向對轉態特性的影響。利用濺鍍法直接將鎳酸鑭薄膜成長於SiO2/Si基板可以得到(100)和(200)優選方向的鎳酸鑭底電極。利用製程條件控制成長(110)優選方向的鈦酸鍶薄膜，再將鎳酸鑭薄膜成長於上，則可得到(110)優選方向的鎳酸鑭底電極。再利用濺鍍法將鋯酸鍶薄膜成長於鎳酸鑭底電極上可以分別得到(100)、(200)的鋯酸鍶薄膜和(110)的鋯酸鍶薄膜。可以發現(100)、(200)的優選方向薄膜具有較佳的電阻轉態特性。

第七章為利用凝膠法來成長鋯酸鍶薄膜，其薄膜具有可重複操作的電阻轉態特性，其轉態速度可提升至僅需要5微秒以下。可以發現其轉態的時間可以累積以達到轉態目的，其轉至高電流狀態之後的電流衰減與轉態的時間和偏壓方向有關。最後並對其高電流狀態的面積效應作一探討，發現其轉態之機制可能是由形成的絲狀物通道所主導。

最後對全文作摘要，並對未來可行的研究工作做一建議。

Perovskite materials have been widely investigated for many applications. In this thesis, the perovskite material was adopted to study the applications on semiconductor memories. For 1T FRAM, the structure was changed from metal/ferroelectric/ semiconductor (MFS) to metal/ferroelectric/insulator/semiconductor (MFIS) and metal/ferroelectric/metal/insulator/semiconductor (MFMIS). The insulator served as a buffer layer needs a high dielectric constant to reduce the operation voltage and low leakage current to increase the retention time. The requirements of the insulator are the same with those of the high-k gate dielectric. Following the international technology roadmap of semiconductor (ITRS), the conventional SiO2 gate oxide thickness is required to be less than 2 nm in the near future. However, as the oxide thickness is scaled down to below 2 nm, the gate leakage current increases significantly due to the direct tunneling, leading to undesired power consumptions in CMOS devices. As a result, many high-k gate dielectrics have been investigated as potential replacements for SiO2 to provide a physically thicker film to reduce the leakage current. In addition, recently the perovskite films have also been investigated for nonvolatile memory application, which is called as resistance random access memory (RRAM). The RRAM with the properties of the reversible switching between the low and the high leakage-states, and the multilevel switching is a promising candidate for nonvolatile memory applications. Chapter 1 introduces that the high-k gate dielectric is necessary for the future CMOS. Many requirements of high-k gate dielectric were described. The RRAM is also introduced. The material groups, fabrication structure, operation method, and switching mechanisms of RRAM were also described. The procedures of fabrication of samples, and the physical and electrical measurements were described in chapter 2. Chapter 3 studied the electrical properties of SrTiO3 gate dielectrics on Si substrates grown by radio-frequency magnetron sputtering. The surface nitridation and repeated spike heating were employed to improve the interfacial properties of SrTiO3/Si. The experimental results indicate that this nitridation treatment may retard the formation of thin interfacial layer during the high temperature growth of SrTiO3 gate dielectric and consequently decrease the equivalent oxide thickness (EOT). The SrTiO3 gate dielectric with nitridation treatment exhibited slightly lower leakage current at accumulation region and nearly 2 orders of magnitude lower leakage current at inversion region. The repeated spike heating technique was also employed to deposit SrTiO3 gate dielectric at repeated oscillating temperatures. These results show that this thermal treatment reduced the interfacial trap states and the leakage current was also reduced by about 1 order of magnitude at the same EOT. Chapter 4 investigated the relation between the capacitance-voltage (C-V) characteristics and current-voltage (I-V) characteristics. SrTiO3 thin films were deposited on silicon substrate by radio-frequency magnetron sputtering in an Ar-O2 and Ar-N2 mixed ambient to form metal/insulator/semiconductor structure. It was observed that the generation current dominated the leakage mechanism at the high electric field under positive bias voltage due to the highly leaky insulator and the lack of electrons. To maintain the leakage current at the higher electric field, the depletion width would broaden to generate more electrons, which is called as deep depletion. Therefore, the deep depletion was induced by high leakage current density under positive bias voltage. The correlation between the deep depletion and the leakage mechanism under positive bias voltage was investigated to extract the generation lifetime of silicon substrate. The extracted generation lifetime can be used to examine the quality of silicon substrates under different processing conditions. Sputter-deposited Cr-doped SrZrO3-based metal-insulator-metal (MIM) structure exhibited bistable resistive reversible switching as observed under bias voltage and voltage pulse, as described in chapter 5. The ratio of resistance of the two leakage-states was about five orders of magnitude. The conduction of the low-state satisfied Frenkel-Poole emission and that of the high-state followed ohmic mechanism, causing the resistance ratio to decrease with increasing bias voltage. The transition time of high to low-state was five orders of magnitude higher than that of low to high-state. The transition from high to low-state was the restricted part for reversible switching operation. The difference in transition time of the two leakage-states should be related to the respective conduction mechanisms. The influence of SrZrO3 film orientation on electrical properties was investigated in chapter 6. Sputter-deposited V-doped SrZrO3 films were deposited on LaNiO3 bottom electrodes with different preferred orientations. The Al/V-doped SrZrO3/LNO sandwich structures with different preferred orientation SZO films were formed to investigate their electrical properties. The device with (100) and (200) preferred orientation SrZrO3 film had better resistive transition properties than that with (110) preferred orientation SrZrO3 film. Chapter 7 described the metal/insulator/metal structures that were fabricated by using sol-gel derived SrZrO3 thin films to demonstrate the reversible resistance switching property which can be operated by dc voltage sweep and voltage pulse. The physical and electrical properties of the MIM device are studied. The resistance of the device changes from original-state to high-state, which is called as forming process and needs larger switching voltage. The switching time can be accumulated to switch the device from high-state to low-state. The decay behaviors of leakage current after resistance switching by voltage pulses are affected by pulse width and polarity of voltage stress. The decay of the leakage current density decreases with increasing pulse width. In addition, the decay of the leakage current density increases while the polarity of the voltage pulse is not the same with that of voltage stress. Furthermore, the leakage current of high-state does not vary with increasing area of the top electrode. The switching behaviors may be attributed to the formation of conducting filaments of the high-state. Finally, the experimental results were summarized. Some suggestions for future work were also provided. Furthermore, some relative interesting topics were also described.