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dc.contributor.author陳弘昕en_US
dc.contributor.authorChen, Hung-Hsinen_US
dc.contributor.author趙家佐en_US
dc.contributor.authorChao, Chia-Tsoen_US
dc.date.accessioned2014-12-12T01:37:34Z-
dc.date.available2014-12-12T01:37:34Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711629en_US
dc.identifier.urihttp://hdl.handle.net/11536/44329-
dc.description.abstract因應更低電壓系統的要求,有很大量的研究已經花在如何發展一個有效並且更經濟使用次臨界電壓的靜態隨機存取記憶體設計上。然而在測試方法上,考慮到最新發展使用次臨界電壓的靜態隨機存取記憶體設計還尚未完全被討論完。因此,我們首先對很多使用次臨界電壓的靜態隨機存取記憶體設計分成三大類設計,並且研究每一種分類上的設計的開路缺陷的錯誤行為模式。並且針對這些錯誤可能會或是不會被傳統靜態隨機存取記憶體的測試方法所測到錯誤。針對於較難測到的錯誤,我們會更進一步討論不同分類的次臨界電壓的靜態隨機存取記憶體設計所對應的測試方法。最後,討論溫度在測試上需要怎運作。zh_TW
dc.description.abstractDue to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold-SRAM design. However, the test methods regarding those newly developed subthreshold-SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold-SRAM designs into three types, study the faulty behavior of different open defects for each type of designs, and then identify the faults which may or may not be covered by a traditional SRAM test method. For those hard-to-detect faults, we will further discuss the corresponding test method according to different each type of subthreshold-SRAM designs. At last, a discussion about the temperature at test will also be provided.en_US
dc.language.isoen_USen_US
dc.subject臨界電壓zh_TW
dc.subject測試方法zh_TW
dc.subject靜態隨機存取記憶體zh_TW
dc.subject斷開缺陷zh_TW
dc.subjectsubthresdhold voltageen_US
dc.subjecttest methoden_US
dc.subjectSRAMen_US
dc.subjectopen defecten_US
dc.title測試次臨界電壓的靜態隨機存取記憶體的開路zh_TW
dc.titleTesting Open Defects for Subthreshold SRAM designsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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