奈米級CMOS靜態隨機存取記憶體之負/正偏壓溫度效應劣化現象與雜訊邊界量測電路

Abstract

生命週期可靠度對於設計一個可靠的VLSI系統而言是個關鍵的設計要素。對於奈米級CMOS VLSI系統之性能與良率而言，偏壓溫度不穩定效應、熱載子注入效應和時間相依介電質崩潰效應已成為其主要考量。靜態隨機存取記憶體(SRAM)已成為單晶片系統(SoC)設計中相當重要的一環。傳統的6T cell，在因製程變動和其他元件可靠度效應造成的可靠度議題中面臨到嚴厲的挑戰。由於SRAM的操作特性，使得在各種效應當中，偏壓溫度不穩定效應對於一個穩定且可靠的SRAM設計來說是最重要的一個議題。 在本篇論文當中，我們提出了一個負/正溫度偏壓不穩定效應測試電路與流程，用以分析奈米級CMOS SRAM的可靠度劣化效應。首先，我們提出SRAM 環形振盪器(Ring Oscillator) 量測負/正溫度偏壓劣化效應。此外，我們更提出一個全數位且內嵌於晶片上的6T SRAM雜訊邊界測試電路。這個電路可量測出靜態雜訊邊界與寫入邊界，並且能達到統計上的量測結果。兩個量測電路均已使用UMC 55奈米SPRVT CMOS製程下線製作晶片。內嵌式SRAM 環形振盪器達到量測到環形震盪器15%的震盪頻率變化的目標。而，陣列式的雜訊邊界量測電路更可提供精準度高達0.167mV的數位輸出介面。

Lifetime reliability is one of the key design factors for robust VLSI systems. Bias Temperature Instability, Hot Carrier Injection, and Time Dependent Dielectric Breakdown have become major concerns for performance and yield of nano-scale CMOS VLSI systems. Static Random Access Memory (SRAM) plays a significant role in the System on Chip design. The conventional 6T SRAM cell faces severe challenges on reliability issues due to process variations and some device reliability effects. Among those effects, Bias Temperature Instability is the most important one for a robust SRAM design due to the features of SRAM operation. In this thesis, we propose a NBTI/PBTI testing structure and measurement flow to analyze the reliability degradation in nano-scale CMOS SRAM. First, SRAM Ring Oscillator (SRAM RO) is presented for measuring NBTI/PBTI degradation. Then, we introduce an all-digital on-chip testing circuit for noise margin of 6T SRAM. This circuit can measure out the read static noise margin and write margin, and can make statistical measurement results. Both two measurement/monitoring circuits has been implemented in UMC 55nm SPRVT CMOS technology. Embedded SRAM ring oscillator can achieve the goal to detect 15% of frequency difference between ring oscillators. Array based measurement circuit for noise margin can provide a digital read-out circuit with 0.167mV resolution in LSB.