一個低功率低雜訊可攜式的類比前端心電訊號量測系統

Abstract

由於社會邁向高齡化及對醫療品質的要求提升，因應這樣的趨勢，近年來，遠距醫療不斷的被提倡，而希望達成遠距醫療的願景，就必須先建立一套小尺寸、便於攜帶的生理訊號量測系統。而這套系統內最重要的區塊即為類比前端電路(Analog Front-End)；因為它決定了我們的訊號品質有沒有被擷取的價值。 在此，我們實現了一組可量測心電訊號的前端電路，提升效能的關鍵在於使用了AC耦合(AC-Coupling)及Chopping的電流回授偏差可抵消的儀表放大器(Current-Feedback Instrumentation Amplifier with Offset Cancellable)；放大器設計採低功率(10x μA)並進一步增強放大器的增益線性度。 此外，AC-Coupling可有效阻隔偏差(Offset)，不論是電路本身不匹配(Mismatch)造成的偏差；或是約幾十mV，由AgCl貼片造成的偏差。前端電路的CMRR值可達120dB以上。Chopping則將1/f雜訊調變至高頻並濾除；然而，Chopping卻同時使訊號上產生突波(Spike)，為我們所不樂見的，所以透過濾波器(Chopping Spike Filter)消除。最後，透過一個外部數位可調增益及可調頻寬的放大器，設定整體前端電路的增益及頻寬。 此電路採用TSMC 0.18 μm CMOS製程技術，操作電壓1.8 V，總面積為 1.1 X 1.08 mm2，整體功率消耗少於20 μW。

Due to aging population and increasing demands about the quality of medical treatment, remote medical treatment has been promoted constantly. However, to achieve the vision, we need to establish an acquisition system for physiological signals, which is small-size and portable. The most important block of the acquisition system is analog front-end. Because it determines whether the quality of signals are worthy of acquisition. In this work, an analog front-end circuit for ECG (Electrocardiogram) acquisition is implemented. Key to its performance is the AC-coupled chopped instrumentation amplifier, which uses current feedback to reject offset. Low power techniques are applied to amplifier design and further enhance the gain linearity of the amplifier. Moreover, offset either caused by circuit mismatch or caused by differential electrode, which is up to several tens of mV from AgCl electrodes, could be rejected effectively. The amplifier achieves more than 120dB CMRR. Chopping could modulates 1/f noise to high frequency band, hence the 1/f noise was filtered by the limited bandwidth of the next stage amplifier. However, we wouldn’t like to see that spikes in company with signal caused by chopping simultaneously; So, we need a chopping spike filter to get rid of them. Finally, we set up the gain and bandwidth of the whole analog front-end circuitry by means of a gain and bandwidth externally tunable amplifier in the last stage. Implemented in a 180nm CMOS technology, the area is 1.1x1.08 mm2 including PAD, the chip consumes less than 20 μW from 1.8V supply.