标题: 用于矽穿孔之三维积体电路完整电源供应之分析
Power Integrity in TSV 3D Integration
作者: 林天鸿
Lin, Tien-Hung
黄威
Hwang, Wei
电子研究所
关键字: 电源供应;杂讯抑制;三维积体电路;矽穿孔;Power integrity;TSV 3D
公开日期: 2009
摘要: 三维积体电路不但非常适合異质整合,更能够提升系统整体的速度以及降低功率消耗。然而当大量的电流同时流过封装及矽穿孔(TSV)所造成的杂讯是非常可怕的,因此如何设计一个稳定的电源供应系统是非常重要的。在本篇論文中,我们提出了一个有效率的设计电源矽穿孔(power TSV bundle)的方法。并且根据矽穿孔之三维积体电路的特性提出了一个使用主动藕荷电容的电源杂讯抑制的电路机制。最后提出一个低静态电流的低压降线性稳压器(LDO)提供可调的低杂讯电源供应电压,并使用基底杂讯抑制的机制來减少藉由基底所传出的杂讯。利用UMC 65nm CMOS 以及TSV模型技术來实现电路设计与布局。
Three-dimensional (3D) nanosystems can provide enormous advantages in achieving multi-functional integration, improving system speed and reducing power consumption for future generations of ICs. The robust power delivery system is very important in 3D ICs. In 3D integration, the increasing supply current through both package and through-silicon-via (TSV) would lead to a large simultaneous switching noise potentially. We will introduce basic 3D technology and a proposed design method for placing the TSV bundle in 3D IC under the efficiency condition. Next, the active supply noise regulation scheme is introduced; we propose the power noise suppression technique using active decoupling capacitor (DECAPs) for TSV 3D integration characteristic. Finally, a low quiescent current linear drop regulator (LDO) is proposed to provide difference supply voltage with low noise, and substrate noise canceller is used to suppress the impact of substrate noise. All simulations are based on UMC 65nm CMOS technology and TSV model at 1V supply voltage.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079711650
http://hdl.handle.net/11536/44351
显示于类别:Thesis


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