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dc.contributor.author林宜緯en_US
dc.contributor.authorLin, Yi-Weien_US
dc.contributor.author莊景德en_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2015-11-26T01:05:20Z-
dc.date.available2015-11-26T01:05:20Z-
dc.date.issued2010en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711665en_US
dc.identifier.urihttp://hdl.handle.net/11536/44366-
dc.description.abstract對於幾乎現今所有的電子設備都必須要用到記憶體來當作儲存媒介,於是記憶體的操作效能變掌握了整個系統的操作速度。而因為靜態隨機存取記憶體有著比其他記憶體種類更高的操作速度,靜態隨機存取記憶體通常會被嵌入到系統當中做為儲存媒介或者是快取記憶體。過去20年當中,6T靜態隨機存取記憶體因為有比較緊密的面積以及較高的操作速度而變成靜態隨機存取記憶體設計的主流。然而當製程進行到一百奈米等級之後,製程變異讓6T靜態隨機存取記憶體變得很難存活。先進製程中,6T靜態隨機存取記憶體的讀取和寫入能力都遭受到很大的退化。特別是低壓操作,6T靜態隨機存取記憶體能夠正常運作的機率就又更小了。 為了要使6T靜態隨機存取記憶體能夠正常的在先進製程下工作,我們提出了兩個電路技巧: WL降壓以及資料依存性寫入幫助電路來幫助讀寫能力。而讀寫的雜訊限度都會得到提升。即使在低壓操作,128k位元的6T靜態隨機存取記憶體測試晶片依然能夠操作。此外,我們另外實現了一個監測電路來對6T靜態隨機存取記憶體的變異以及雜訊限度來做特性化。512位元的測試陣列可以提供我們足夠的資料量來分析其統計上的分佈。而陣列的實現方式可以使得到的資訊能夠很接近真實的6T靜態隨機存取記憶體陣列而不是僅僅從模擬上得到。而配合特別設計的的量測方法,可以是我們的解析度達到某個程度,也可以自動化的量測。zh_TW
dc.description.abstractAlmost the modern electronic devices need memory as its storage media, and the performance of memory always dominant the overall performance of one system. Since SRAM has highest operating speed than other memory family, it is usually embedded into system to storage data or to be a cache. From past decades, standard 6T cell becomes the main stream of SRAM design due to its compact area and high speed. However, as the technology goes beyond 100 nm, variation issue makes 6T SRAM cell hard to survive. The Read/Write ability suffers a serious degradation in advanced technology node. Especially at low voltage, 6T SRAM seem has smaller probability to work. In order to successfully allow 6T SRAM work at advanced process, we proposed two circuit techniques : Word-Line Under-Drive and Data-Aware Write-Assist to increase the read and write ability. Both Read Static Noise Margin and Write Margin would be improved. Even at low voltage operation, the test chip of one 128kb 6T SRAM still function work. Besides, we implement a monitoring structure to characterize the variation factors and noise margin of 6T cells. The test Array has 512kb cells could provide us a sufficient amount sample to analysis the statistical distribution. The Array Based implementation could allow us to get the information about Noise Margin quite close to real SRAM macro rather than get it just from simulation. And with a special designed measure scheme, the measurement resolution could be guaranteed and the measurement could be automatic.en_US
dc.language.isoen_USen_US
dc.subject靜態隨機存取記憶體zh_TW
dc.subject低字元線電壓zh_TW
dc.subject資料依存性寫入輔助電路zh_TW
dc.subject製程變異zh_TW
dc.subject監控電路zh_TW
dc.subject靜態雜訊邊界zh_TW
dc.subject讀取干擾電壓zh_TW
dc.subjectStatic Random Access Memoryen_US
dc.subjectSRAMen_US
dc.subjectWord-Line Under-Driveen_US
dc.subjectData-Aware Write-Assisten_US
dc.subjectkeeperen_US
dc.subjectvariaitonen_US
dc.subjectmonitor structureen_US
dc.subjectStatic Noise Marginen_US
dc.subjectSNMen_US
dc.subjectread disturb voltageen_US
dc.subjectVreaden_US
dc.subjectVtripen_US
dc.title6T靜態隨機存取記憶體的設計與特性分析zh_TW
dc.titleDesign and characterization of 6T SRAMen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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