應用於交叉點八電晶體靜態隨機存取記憶體之資料感知動態電源寫入輔助之分析與設計

Abstract

因為在許多半導體記憶體技術中具有最快的存取速度，靜態隨機存取記憶體在眾多系統單晶片的設計，扮演著重要且不可或缺的角色。也因為記憶體在晶片中時常佔據大比例的面積，具有可在低壓操作的靜態隨機存取記憶體能使整體系統的功耗大幅下降。隨著製程與技術演進縮小，嚴重的製程變異使得元件特性漂移且威脅了數位電路的操作性能。在此論文中，提出具有資料感知動態電源寫入輔助技巧，應用於具有交叉點特性的八電晶體靜態記憶胞並且設計128Kb大小的晶片。此技巧在操作電壓介於0.5伏特與0.8伏特之間時，平均上達到寫入邊界超過20%的操作電壓，並且以具有對抗製程變異卻花費非常小的晶片面積為其主要特點。同樣地，在操作電壓介於0.5伏特與0.8伏特之間時，寫入性能也從原本甚至寫入失敗達到了皮秒的等級。模擬結果顯示出，此晶片能在操作電壓0.6伏特時達到474MHz的操作速度。

With fastest access speed among semiconductor memories, embedded Static Random Access Memory (SRAM) plays an important role in various System-on-Chip (SoC) designs. Due to its large ratio, low voltage operation capability of SRAM can lower the total system power significantly. But technology scaling, variation severely degrades functionality of digital circuit. In this thesis, a Data-Aware dynamic supply Write-Assist scheme is proposed and implemented with 128Kb cross-point 8T SRAM. This technique improves Write margin over 20% on average at operating voltage ranges from 0.5V to 0.8V, and features good anti-variation ability with minimum area overhead. Meanwhile, Write performance improves to pico-second scale, otherwise would fail if no Write assist technique is applied, on average at operating voltage ranges from 0.5V to 0.8V. Simulation results show that chip operation speed achieves 474MHz at VDD = 0.6V.