完整後設資料紀錄
DC 欄位語言
dc.contributor.author蔡竣揚en_US
dc.contributor.authorTsai, Chun-Yangen_US
dc.contributor.author荊鳳德en_US
dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-12T01:37:48Z-
dc.date.available2014-12-12T01:37:48Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079711801en_US
dc.identifier.urihttp://hdl.handle.net/11536/44385-
dc.description.abstract近年來為了有效降低晶片面積和節省成本,邏輯與記憶體元件必須不斷的微縮。在奈米元件中,傳統的介電質材料將面臨物理極限。在此情況下,高介電係數介電質材料的研究似乎成為唯一的選擇。對於非揮發性記憶體而言,當元件不斷微縮至二十奈米,金屬-氧化層-氮化層-氧化層-矽(MONOS)電荷捕獲(Charge-Trapping)非揮發性記憶體將用來取代多晶矽(poly-Si)懸浮閘(Floating-Gate)記憶體。在不斷微縮垂直閘極堆疊厚度下,如何有好的電荷捕獲控制能力將是電荷捕獲記憶體面臨最主要的挑戰。然而,當氮化矽捕獲層厚度微縮至三奈米,其電荷捕獲效能、資料記憶視窗和資料保存特性將嚴重的衰退,為了改善電荷捕獲能力和資料保存性,使用具有深導帶能階(EC)的高介電係數介電質材料捕獲層是必要的。對未來的金屬-絕緣層-金屬(MIM)電容而言,擁有高電容密度和保有低漏電流是必要的,此外,介電質厚度需小於十奈米才能符合三度空間微縮的DRAM結構。在本論文中,吾人將探討數種高介電係數介電質材料在電荷捕獲記憶體和金氧金電容上的應用。 首先,我們研發出一種氮化鉭(TaN)-氧化矽(SiO2)-氧化鋁鑭(LaAlO3)-氮氧化鉿(HfON)-氧化鋁鑭(LaAlO3)-氧化矽(SiO2)-矽(Si)的電荷捕獲記憶體。此元件在快速100毫秒和電壓16伏特的操作條件下,具有6.4伏特的初始資料記憶視窗、在125oC下,乃有4.3伏特的十年資料儲存能力並具有106次的寫入/抹除的資料耐久性。此記憶體元件特性主要來自於使用砷(As)離子佈植至氮氧化鉿(HfON)捕獲層中,相較於未使用砷(As)離子佈植的元件特性有很大的差異。為了微縮等效氮化矽厚度(ENT),我們將砷(As)離子佈植的氮氧化鉿(HfON)換成砷(As)離子佈植的氮氧化鋯(ZrON),此記憶體元件在相同的操作條件下,可得到3.6奈米的高度微縮等效氮化矽厚度(ENT)、4.9伏特的初始資料記憶視窗和在125oC下乃有3.1伏特的十年資料儲存能力。 其次,為了更進一步的微縮等效氮化矽厚度(ENT),我們使用了鍺(Ge)與氮氧化鉿(HfON)捕獲層反應,形成氮氧化鍺鉿(HfGeON)來有效增加電荷捕獲能力和資料保存性。此電荷捕獲記憶體擁有極薄2.5奈米的等效氮化矽厚度(ENT)、4.9伏特的初始資料記憶視窗、在125oC下乃有3.2伏特很好的十年資料儲存能力和經106次的寫入/抹除後乃保有3.6 V的資料耐久性。 最後,對於金氧金(MIM)電容的應用,我們提出使用雷射退火製作出鎳(Ni)/氧化鋯(ZrO2)/氮化鈦(TiN)的金氧金電容結構,此電容具有52 fF/um2的高電容密度、1.6*10-7 A/cm2的低漏電流和1.7%的微小十年電容穩定性變動。此元件製成主要歸功於使用雷射退火來增加提升氧化鋯(ZrO2)的四角形相(tetragonal-phase)、和高功函數金屬鎳(Ni)電極和良好底層介面處理。zh_TW
dc.description.abstractRecently, the logic and memory devices size are being continuously scaled down to reduce the area of the chip and the cost. However traditional dielectric materials will face the physical limitation of nano devices. To meet this requirement, high dielectric constant (k) materials provide the only solution. For nonvolatile memory, to continue downscaling into sub-20-nm region, the metal-oxide-nitride-oxide-Si (MONOS) Charge-Trapping (CT) flash devices will be used to replace the poly-Si floating-gate (FG) flash memory. One difficult challenge for CT flash is to scale down the vertical gate stack for better charge control. However, the charge-trapping efficiency, memory window and retention characteristics are largely degraded at the target 3-nm Si3N4 trapping layer. To improve the charge-trapping efficiency and retention is to use a deep conduction band energy (EC) high-k trapping layer. For future generation Metal-Insulator-Metal (MIM) capacitors, higher capacitance density with still low leakage current is required. Besides, small dielectric thickness less than 10 nm is demanded to fit in the scaled three-dimensional DRAM structure. In this dissertation, we will investigate the application of several high-k dielectric materials for CT flash memory and MIM Capacitors. First of all, we have fabricated the TaN-[SiO2-LaAlO3]-HfON-[LaAlO3-SiO2]-Si Charge-Trapping (CT) flash device. A Large 6.4 V initial memory window, a 4.3 V 10-year extrapolated retention window at 125oC, and a 5.5 V endurance window at 106 cycles were measured, under very fast 100 us and low 16 V program/erase (P/E). These excellent results were achieved using As+ implant into HfON trapping layer that were significantly better than those of control device without ion implantation. In order to downscale the equivalent-Si3N4-thickness (ENT), we also have replaced As+-implanted HfON with As+-implanted-ZrON trapping layer. The device has a highly scaled 3.6 nm ENT, a large 4.9 V initial memory window, and a good retention of 3.1 V 10-year extrapolated retention window at 125oC, under the same P/E conditions. Next, to further downscale the ENT, we also used Ge reaction with HfON trapping layer to form HfGeON for better charge-trapping and data retention. This CT flash device with record-thinnest 2.5-nm ENT trapping layer, a large 4.4 V initial memory window, a good retention of 3.2 V 10-year extrapolated retention window at 125oC, and endurance window of 3.6 V at 106 cycles were measured. Finally, for MIM capacitors, we also have fabricated high-κNi/ZrO2/TiN MIM capacitors with a very high 52 fF/um2 capacitance density, a low leakage current of 1.6*10-7 A/cm2 and good 10-year reliability with a small □C/C of 1.7% at 2 V. Such excellent device integrity is attributed to the combination of enhanced ZrO2 tetragonal-phase by laser annealing, high work-function Ni electrode and good bottom-interface treatment.en_US
dc.language.isoen_USen_US
dc.subject非揮發性記憶體zh_TW
dc.subject電荷捕獲記憶體zh_TW
dc.subject金氧金電容zh_TW
dc.subjectnon-volatile memoryen_US
dc.subjectcharge-trapping flashen_US
dc.subjectMIM capacitoren_US
dc.title高度微縮等效氮化矽厚度之電荷捕獲記憶體和金屬-絕緣層-金屬電容結構之研究zh_TW
dc.titleThe Investigation of Novel High-Scaled Equivalent-Si3N4-Thickness Charge-Trapping Flash and Metal-Insulator-Metal Capacitoren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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