可寫入抹除高介電常數氮氧化鉿金屬-絕緣層-矽 電容

Abstract

記憶體電容是決定檢測訊號電壓、速度、資料保存時間、耐久性以及防止軟性誤差的重要參數。然而隨著超大型積體電路技術不斷的微縮，電容面積勢必隨之遞減，以期達到減少元件尺寸及降低成本的需求，但此舉將減低電容厚度造成不必要的漏電流，為了解決此問題，傳統的二氧化矽將被高介電常數材料所取代，以達高電容密度及降低漏電流，此外記憶體電容也渴望具有可寫入抹除和良好資料保存等特性。 本文將探討使用高介電常數氮氧化鉿為介電層的 可寫入抹除 金屬-絕緣層-矽 結構電容，其可應用在記憶體上例如:動態隨取記憶體(DRAM)與快閃記憶體(Flash)。此元件具有高電容密度約6.5 fF/mm2、低寫入-抹除電壓 ±5V、大記憶體視窗1.5V以及優異資料保存特性。此外經由漏電流特性分析計算出其蕭基能障與電子捕捉能階，發現氮氧化鉿蕭基能障為0.69~0.7 eV且具有較深的電子捕捉能階約1.01~1.05 eV。

Memory cell capacitance is the crucial parameter which determines the sensing signal voltage, speed, data retention times, endurance and against the soft error event. However, the very large scale integration (VLSI) technology is continues down-scaling of the size of capacitors to reduce chip size and the cost. It will decrease dielectric thickness and result in the undesired leakage current. To solve this problem, the conventional silicon dioxide will be replaced with high dielectric constant (high-k) materials to increase the capacitance density and degrade the leakage current. Besides, capacitors also desire both good data retention and program-erasable capability for memory applications. In this study, we demonstrate a programmable-erasable MIS capacitor with a single high-k Hf3N2O5 dielectric layer for many applications such as volatile DRAM and non-volatile MONOS type memories. This device showed a capacitance density of ~ 6.5 fF/mm2, low program and erase voltages of +5 and -5 V, and a large Vth memory window of 1.5V. In addition the 25oC data retention was good, as in program and erase decay rates of only 2 and 6.2 mV/dec. In addition, we found a deep trapping level of 1.01~1.05 eV from measured J-V characteristics. The electrodes displayed a Schottky barrier height of 0.69~0.7 eV.