新穎多閘極多晶矽奈米線薄膜電晶體之研製與其應用

Abstract

在本篇論文中，我們利用數種簡易的奈米線製備技術，製作並研究各式具有多閘極結構的多晶矽奈米線薄膜電晶體。所提出的多閘極奈米線電晶體製備方式包括"側壁邊襯蝕刻法(side-wall spacer etching)”與”空腔形成填充法(cavity formation and filling)”，使用此兩種製備方式均可免除昂貴的微影設備與製作技術，自我對準形成各式高效能的多晶矽奈米線通道電晶體。 首先，我們針對使用側壁邊襯蝕刻技術所製作的雙獨立閘極多晶矽奈米線電晶體，探討在不同操作模式下(雙閘或單閘)之元件特性。由於奈米線通道厚度僅有約10奈米，強烈的閘極耦合效應(gate-to-gate coupling)會對元件電性造成深切的影響。在雙閘操作模式下，此元件可達到小於100mV/dec之次臨限擺幅(subthreshold swing)；而在單閘模式下，利用閘極耦合效應來調整輔助閘偏壓的方式可獲得不同的臨限電壓。實驗中我們也發現，在雙閘模式下由於不受背閘極效應(back-gate effect)的影響，在輸出特性上會有比單閘操作高之飽和汲極電壓，因此可獲得較大之飽和輸出電流(output saturation current)；此外，在雙閘操作下對於通道中晶粒邊界與缺陷所造成之位能障(grain-boundary potential barrier)具有較佳的調控能力，因而可獲得較單閘操作下為佳之元件特性。此發現對於分析多晶矽通道元件之傳導機制具有重要的影響。我們也探討了雙獨立閘極多晶矽奈米線電晶體的基本電性擾動分析。從實驗數據顯示，利用電漿處理修補多晶矽通道裡的缺陷，可使元件之間的臨限電壓差異性降低，由此推測出複晶矽奈米線通道中的缺陷密度與電性擾動有一密切的關聯性。另外，在不同的操作模式下(雙閘或單閘)，以雙閘極操作模式，可得到最小的臨限電壓標準差。由於元件間通道厚度的差異所造成的臨限電壓擾動，會隨著橫跨在通道薄膜之電場大小而不同；實驗中也證實，當在單閘操作模式下，控制閘極的固定偏壓存在著一最佳值，能有效地降低臨限電壓的變異度。 除了使用側壁邊襯蝕刻法製作奈米線元件，我們也提出並發展了另一種新穎的奈米線製備技術，稱作空腔形成填充法。利用此技術製作出的三閘極(tri-gate)多晶矽奈米線電晶體展現了相當陡峭的次臨限擺幅(~100mV/dec)，和大於108的開關電流比值(ON/OFF current ratio)。此結果驗證了多閘極可以有效增進元件的效能。另外，一種基於空腔形成填充法，可以同時製作出具有不同閘極結構但奈米線通道形狀相同之電晶體的製程技術也被提出。利用此簡單有趣的製程，能有效分析與評估多重閘(Multi-gate)的實際效應，且有助於探討多重閘對於奈米線元件的基本特性和及電性擾動的影響。實驗結果亦顯示越佳的閘極控制能力對於奈米線元件之變異度也能越有效的控制。 在非揮發記憶體應用方面，我們利用空腔形成填充法成功地製作了多種閘極型態的SONOS記憶體元件，包含單側閘極(side-gated, SG)、Ω型閘(Ω-gated)和全環繞閘極(gate-all-around, GAA)。其中全環繞閘極奈米線記憶體元件除了展現出最佳的基本電性，記憶體特性方面包含寫入/抹除速度、電荷保持能力(retention)和忍耐力(endurance)也具有很顯著的增進。這些實驗結果都歸因於全環繞閘極奈米線電晶體擁有接近理想的圓形奈米線通道截面，和最有效的閘極控制能力。 在論文的最後部份，我們提出並製作一種具有延伸式感測閘(SENSE-gate)與讀取閘(READ-gate)的新穎雙獨立閘極奈米線感測元件，並對於各種感測應用的可行性進行初步的探討。此感測架構結合奈米線電晶體結構與延伸式閘極離子感測場效電晶體(EGFET)的概念，可有效將元件操作區與充滿酸/鹼性化學物質或生物分子溶液的感測區與隔離。因此所製作出之感測元件，同時具有延伸式閘極感測元件之可靠度與系統整合能力，還有奈米線感測元件之優良的轉導特性。此研究也呈現並討論各種實際感測的初步實驗結果，包括酸鹼感測(pH sensing)、生物分子偵測(bio-molecules detection)和氣體感測(gas sensing)。另外，相較於把多晶矽奈米線直接曝露在環境中作感測的感測元件，此雙獨立閘感測元件由於使用了延伸式閘極結構，在中性水溶液環境中的施壓測試(stressing testing)中明顯展現更穩定與可靠的電性結果。

Various multiple-gated (MG) polycrystalline silicon nanowire (poly-Si NW) thin-film transistors (TFTs) are fabricated and analyzed. The proposed NWTFT schemes utilize very simple and low-cost NW preparation techniques, including “side-wall spacer etching” and “cavity formation and filling”, to fabricate poly-Si NWs in a self-aligned manner. Detailed characteristics of the MG NWTFT devices and their potential applications involving non-volatile memory (NVM) and chemical sensors are also studied and demonstrated. For NW devices fabricated by the side-wall spacer etching technique, the characteristics of the poly-Si NWTFT featuring an independent double-gated (DG) configuration are analyzed and compared. It is found that the device under DG mode exhibits significantly better performance with respect to the two single-gated (SG) modes in terms of a higher current drive over the combined sum of the two SG modes and a smaller subthreshold swing (SS) of less than 100 mV/dec. Origins of such improvement are identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with DG operation. The mobility improvement in DG mode is ascribed to more efficient gate control in lowering the grain-boundary potential barrier. Moreover, the VTH fluctuation behavior of poly-Si NWTFTs is also investigated and studied. The defects existing in the NW channels are identified as one of the major sources for the VTH fluctuation. The passivation of these defects by plasma treatment is shown to be effective in reducing the VTH fluctuation. It is also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the device’s switching behavior, an optimum bias for the other gate could be found for minimizing the VTH fluctuation. On the development of new NW preparation method, the cavity formation and filling technique is proposed, which enables the fabrication of poly-Si NW without resorting to advanced lithographic tools. The tri-gated poly-Si NWTFTs built on this novel technique show steep SS of around 100 mV/dec and ON/OFF current ratio higher than 108, signifying the effectiveness of MG scheme in improving the device performance. Furthermore, a clever scheme based on cavity formation and filling technique allowing fabricating test structures with identical NW channel but different gate configurations is also proposed, and the impact of MG configurations on the variation of NWTFTs characteristics is also investigated. The results show the variation is reduced by increasing the portion of NW channel surface that is modulated by the gate. As regards NVM applications, we demonstrate the poly-Si NW-SONOS devices using the cavity formation and filling technique. Three types of devices having various gate configurations, namely, side-gated (SG), Ω-shaped gated (ΩG) and gate-all-around (GAA), are successfully fabricated and characterized. The experimental results show that much improved transfer characteristics are achieved with the GAA devices as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest P/E efficiency, largest memory window and best endurance/retention characteristics. Finally, the feasibility of the novel independent DG NW sensing device scheme featuring an extended sensing gate (SENSE-gate) and a READ-gate for various sensing applications is explored. This scheme takes advantages of extended-gate ion-sensitive FET’s (EGFET) effective isolation of device from chemical and biological environment, and NWFET’s good switching properties. The preliminary study using this novel sensing device for pH sensing, gas sensing and bio-molecules detection is presented and described. In addition, owing to the use of extended-gate structure, this novel sensing scheme exhibits more stable and reliable electrical characteristics during the stressing test in aqueous solution as compared with those of NW sensor devices having poly-Si NWs exposed to the ambient.