具有二維晶界控制之多晶矽薄膜與奈米線電晶體於非揮發性記憶體元件之應用與研究

Abstract

高性能低溫多晶矽薄膜電晶體是在低成本玻璃基板上製作高品質之主動式有機發光二極體顯示器，全功能整合系統面板，以及三維積體電路之關鍵元件。隨著系統面板與三維積體電路之發展，完全相容於低溫多晶矽製程之SONOS薄膜電晶體也變得相當受到矚目，此乃因為其能夠有效率地降低系統之功率消耗。準分子雷射退火對非晶矽薄膜進行再結晶可在低溫形成具高結晶性之矽晶粒以達成較佳之元件特性。然而，以準分子雷射退火再結晶方式製備之低溫多晶矽薄膜電晶體雖然具有高的載子移動率，但由於其晶粒邊界及位置是隨機分佈的，因此造成其元件特性之均勻性不佳以至於限制了元件的微縮化。 在本篇論文中，我們提出了三種二維晶界控制方法來製備高性能低溫多晶矽薄膜電晶體並將其應用於SONOS記憶體元件，包括了採用預先定義之底部閘極結構(prepatterned bottom-gate structure)、預先定義之凹陷形通道結構(prepatterned recessed channel structure) 以及非晶矽格子結構(a-Si grids structure)。此外，具有二維晶界控制之奈米線通道元件亦被成功建立來進一步改善元件之特性。 首先，一種利用準分子雷射照射預先定義通道層之底部閘極結構之二維晶界控制法被使用來達成在通道區域中形成十字型之晶界。因此，此預先定義之底部閘極薄膜電晶體之場效載子移動能夠達到339 cm2/V-s，而傳統的頂部閘極薄膜電晶體之場效載子移動只有102 cm2/V-s。同時，由於此可操控之晶粒邊界，此預先定義之底部閘極薄膜電晶體亦具有均勻之元件特性。 其次，利用準分子雷射退火結晶預先定義之凹陷形通道結構之二維晶界控制法來達成在凹陷較薄區域中形成十字型之晶界結構被提出。因此，藉由此晶界結構，垂直於通道方向之晶界能被進一步避免而形成具有單一晶界平行於通道方向之頂部閘極薄膜電晶體。此預先定義之凹陷形通道頂部閘極薄膜電晶體其場效載子移動可以達到412 cm2/V-s，開關電流比高於 1.1 × 108，而傳統的頂部閘極薄膜電晶體之場效載子移動與開關電流比分別為125 cm2/V-s 與2.2 × 107。此外，此預先定義之凹陷形通道頂部閘極薄膜電晶體亦具有明顯比傳統的頂部閘極薄膜電晶體更佳之均勻性。 藉由在區域化增加非晶矽薄膜厚度來作為部分熔融的晶粒成長晶種，十字型的晶界結構可在這些較厚之非晶矽格子間之區域被形成。藉由此二維晶界控制結構，具有單一水平及垂直晶界之多晶矽薄膜電晶體之載子移動率可達到530 cm2/V-s，而開關電流比4 × 108。此外，由於晶界位置能夠被有效的控制，因此，所提出之多晶矽薄膜電晶體亦具有明顯比傳統的頂部閘極薄膜電晶體更佳之均勻性與可靠度。 針對於非揮發性記憶體之開發，具二維晶界控制的多晶矽SONOS薄膜電晶體被成功製備。所製作之具晶界位置控制的多晶矽SONOS薄膜電晶體具有較佳之電晶體特性與記憶體特性。由於具有可控制的突起晶界來加強電場產生較大之穿隧電流，其可在閘極電壓24V之寫入經過1毫秒可達2.27V。另一方面，以二維晶界控制技術為基礎，我們成功評估位於靠近汲極端之晶界對於多晶矽SONOS薄膜電晶體在動態偏壓測試下之影響。實驗結果發現只有在當晶界位於靠近汲極端時，汲極誘導晶粒能障下降效應(drain-induced-grain-barrier-lowing effect)會明顯增加而電晶體關閉電流會明顯下降，這是由於在靠近汲極端晶界處產生了大量的介面態同時伴隨著大量的電洞注入閘極介電層所造成。 為了更進一步改善元件之性能，非晶矽格子結構被利用來製備二維晶界控制奈米線薄膜電晶電晶體具有單一垂直晶界在通道之中，其可具有極佳之載子移動率達到346 cm2/V-s，而開關電流比可達3 × 109。此外，由於其晶界位置是被控制的，二維晶界控制奈米線薄膜電晶電晶體也具備較佳之均勻性及可靠度。再者，在本論文最後一部分，此二維晶界控制方法亦被應用於奈米線多晶矽SONOS薄膜電晶體。實驗結果顯示此具二維晶界控制之奈米線多晶矽SONOS薄膜電晶體擁有較傳統之雷射再結晶方式製備的元件更好的電特性、均勻性、耐久性(endurance) 以及電荷保存能力(data retention)。這些較佳之元件性能可以被歸因於只有單一垂直晶界在通道之中。 在本論文中，高性能二維晶界控制薄膜電晶體與記憶體元件被成功製備，此技術相當適合於應用於未來之系統面板與三維積體電路。

High-performance low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are key devices in the production of high-quality active-matrix organic light-emitting displays (AMOLEDs), full-function system-on-panel (SOP), and three-dimensional integrated circuits (3D-ICs). In the development of SOP and 3D-ICs, the silicon-oxide-nitride-oxide-silicon (SONOS) polycrystalline silicon (poly-Si) TFTs, which can be fully compatible with LTPS process, is also become attractive because they can effectively reduce power consumption of the system. Excimer laser crystallization (ELC) of amorphous silicon (a-Si) can produce high-quality silicon grains at low temperature to lead to superior device performance. However, the LTPS TFTs crystallized by ELC exhibit a high mobility but with the poor uniformity of the device performance because the grain boundaries are randomly distributed and is a critical issue when the device dimension is scaled down. In this thesis, three approaches aiming at the two-dimensional (2D) location control of the grain boundaries, including the adoption of prepatterned bottom-gate (BG) structure, prepatterned recessed channel (RC) structure, and a-Si grids structure, were developed for the high performance LTPS TFTs and the concerned applications in SONOS memory devices. In addition, the nanowire-based (NW-based) devices with the 2D location-controlled grain boundaries were also demonstrated to further enhance the performance of device characteristics. At first, the 2D grain boundary location-controlled method via the excimer laser crystallization on the prepatterned channel layer with the BG structure has been proposed to accomplish the channel region with the cross-shaped grain boundary structure. Consequently, the prepatterned BG TFTs could attain the higher field-effect mobility of 339 cm2/V-s as compared with 102 cm2/V-s for the conventional TG ones. Uniform device characteristics of the prepatterned BG TFTs have been also demonstrated owing to the artificially controlled grain boundaries. Secondly, an ELC method on the prepatterned RC is proposed to achieve the 2D control of the grain boundary location and the resultant cross-shaped grain boundary structures within the recessed regions. Furthermore, the top-gate prepatterned RC TFTs could be also fabricated to avoid the perpendicular grain boundary, namely with only one grain boundary parallel to the channel direction. Such a prepatterned RC TFT exhibited an excellent field-effect mobility of 412 cm2/V-s and an on/off current ratio higher than 1.1 × 108 as compared with 125 cm2/V-s and 2.2 × 107 for the conventional ones, respectively. In addition, the pre-patterned RC TFTs also attained much improvement in the device uniformity with respect to the conventional ones. Thirdly, by using the thicker a-Si thin film as the seed crystals, the cross-shaped grain boundary structures could be produced between the thicker a-Si grids via a partial-melting crystallization scheme. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm2/V-s and on/off current ratio of 4 × 108. Furthermore, the proposed TFTs achieved the much improved uniformity and electrical reliability as compared with the conventional ones owing to the artificially controlled locations of grain boundaries. For the nonvolatile memory development, the 2D grain-boundary-location-controlled (GBLC) poly-Si SONOS TFTs were also demonstrated in this study. The GBLC SONOS devices are proposed to obtain not only better transistor properties but also superior memory characteristics. They can achieve the memory window of 2.27V under the gate voltage of 24V during 1ms programming due to the field-enhanced tunneling at location-controlled grain boundary protrusion. On the other hand, based on the proposed method of location control of grain boundary, the effects of grain boundary near the drain junction on the degradation of SONOS TFT under dynamic voltage stress were examined. It is found that only when the grain boundary is located near the drain junction, the drain-induced-grain-barrier-lowing (DIGBL) effect is apparently increased and the off-state current is remarkably suppressed. This can be attributed to the trap states creation along with hot-holes injection into gate dielectric mainly at the protruding grain boundary near the drain junction during stress. In order to further improve the electrical performance, such a-Si grids structure was also utilized to fabricate the poly-Si NW TFTs with one primary grain boundary perpendicular to the channel direction. The grain-boundary-location-controlled (GBLC) NW TFTs could achieve an excellent field-effect mobility of 346 cm2 /V．s and on/off current ratio of 3 × 109. Furthermore, the GBLC NW TFTs also exhibited superior device uniformity and reliability due to the control of grain boundary locations. Moreover, at last part of this thesis, the 2D grain boundary control technique was also applied to the trigated poly-Si NW SONOS. Our results indicated that the GBLC NW SONOS TFTs exhibited better device electrical characteristics, uniformity, endurance, and data retention characteristics than the conventional ELC ones. The enhanced performance for the GBLC devices could be attributed to the only one primary perpendicular grain boundary perpendicular to the channel direction. In this thesis, the high-performance 2D grain-boundary-controlled poly-Si TFTs and memory devices has been successfully demonstrated. This technology is thus promising for the future applications of LTPS TFTs in system-on-panel (SOP) and 3D-ICs.