EDA和測試方法之於先進CMOS製程技術變異的特性分析與降低化

Abstract

隨著製程技術持續推新進步，製程變異急遽增加並漸漸成為IC製造最關鍵的因素之一。基於design-for-manufacturability的考量, EDA方法中像是dummy fill 和 boolean mask operations等在縮小先進製程變異上都已被驗證是一種很有效率的技術。 然而，在新的先進技術設計上想在首次tape-out便能成功，必須避免過長的處理時間和不夠縝密的驗證流程。另外 從製程開發的角度而言，在先進製程開發階段，常會利用array-based test structure design來量測大量電晶體DUT以監控製程的變異，尋求具統計性、關鍵性的結論。但起因於控制電路影響而造成的測試時間過長及測試結果不準確都會阻礙先進製程開發的挑戰。本論文從EDA, array-based test structure design到參數測試領域提出數種技術來縮小製程變異和改善晶圓設計驗證流程。除此之外，本論文也針對相應的特性測試分析, 快速和高準確度的測試方法進行了多方驗證。

As process technologies continually advance, process variation has greatly increased and gradually become one of the most critical factors for IC manufacturing. Based on design-for-manufacturability considerations, EDA methodologies such as dummy fill and boolean mask operations have been demonstrated to be effective techniques for minimizing advanced process variation. However, long processing time and insufficiently robust verification flows are significant obstacles for delivering functional first silicon on new advanced technology designs. From the process development point of view, to obtain statistically significant and conclusive results, a large number of DUTs using an array-based test structure design is a commonly used technique for variation monitoring at the advanced process development stage. However, long testing time and inaccurate test results due to the influence of the control circuitry pose further challenges for advanced process technology development. This thesis presents several techniques from EDA to parametric testing to minimize process variation, and enhance the verification flow. In addition, the corresponding characterization methodology using an array-based test structure design and a fast and highly accurate testing methodology have been also demonstrated in this work.