一個用以估測導管式類比數位轉換器中殘值放大器多階非線性度的嶄新數位背景複相關估測方法

Abstract

隨著先進製程不斷進步，數位電路因而獲得高速與低功耗的好處。相反地，在先製進製程下因為供應電壓下降、本質增益縮小以及低輸出阻抗等因素，使得設計高效能類比電路的挑戰與日俱增。例如：在先進的CMOS技術下，要設計導管式類比數位轉換器中足夠線性的殘值放大器，變成一項艱鉅的任務。為了解決這些難題，近年許多研究便致力於發展數位校正機制，這些「數位輔助類比電路設計」的核心概念是希望透過穩健的數位電路的幫助來減輕類比電路設計的難度。

本篇論文提出一個可以精確估測導管式類比數位轉換器中殘值放大器多階非線性度的數位背景複相關估測方法。我們利用加入不同振幅的隨機序列，透過一個數位化的相關機制精確地粹取出帶有非線性度的訊息，而且只要使用簡單的數位電路就能實現這個估測方法，藉由這樣的方式能夠有效地降低類比電路設計的複雜度。

我們使用一個第一導管級中的殘值放大器具有多項奇次階非線性失真的十四位元每秒一億次取樣之導管式類比數位轉換器為例。根據模擬結果顯示：在校正前，有效位元(ENOB)為4.9位元、SNDR為31.2dB、SFDR為45.2dBc、INL為+165.50/-166.25LSB、DNL為+11.61/-1.00LSB。透過校正後，ENOB為13.1位元，有高達8.2位元之多的改善。而SNDR及SFDR則分別為80.4dB與94.7dBc，INL與DNL則分別為+0.66/-0.50LSB與+0.55/-0.59LSB。此外我們也模擬其第一導管級的殘值放大器具有多階非線性失真(包含偶次階的非線性)時的情形。模擬結果顯示，於校正前，ENOB為6.4位元、SNDR為40.1dB、SFDR為54.5dBc、INL為+89.79/-55.81LSB而DNL為+6.13/-1.00\\ LSB。經過校正後，此導管式類比數位轉換器具有高達13.9位元的ENOB，而SNDR為85.5\\ dB、SFDR為123.5dBc、INL為+0.46/-0.49LSB、DNL為+0.46/-0.73LSB。經由模擬結果證實，所提出的方法確實能大幅地提升導管式類比數位轉換器之效能。

本篇論文也討論一個用以搭配開迴路架構設計的十二位元每秒一億次取樣導管式類比數位轉換器的數位校正處理器實現電路。模擬結果顯示其數位校正技術能明顯地提升導管式類比數位轉換器的效能。

We use a 14-bit 100MS/s pipelined ADC with a multiple-odd-order nonlinearity residue amplifier in the first pipeline stage as an example. Simulation results show that before calibration, the ADC only has an effective number of bits (ENOB) of 4.9 bits, an SNDR of 31.2 dB, an SFDR of 45.2 dBc, INL values within +165.50/-166.25 LSB, and DNL values within +11.61/-1.00 LSB. After calibration, its ENOB becomes 13.1 bits. A significant 8.2-bit ENOB improvement is achieved. The SNDR and SFDR are 80.4 dB and 94.7 dBc, respectively. The calibrated INL and DNL are +0.66/-0.50 LSB and +0.55/-0.59 LSB, respectively. Simulation results also show that the same model of the pipelined ADC but with a multiple-order (contained with even-order nonlinearity) nonlinear residue amplifier in the first stage before calibration only has an ENOB of 6.4 bits, an SNDR of 40.1 dB, an SFDR of 54.5 dBc, INL values within +89.97/-55.81 LSB and DNL values within +6.13/-1.00 LSB. After calibration, the pipelined ADC has an ENOB of 13.9 bits, an SNDR of 85.5 dB, an SFDR of 123.5 dBc, INL values within +0.46/-0.49 LSB and DNL values within +0.46/-0.73 LSB. The simulation results validate that the proposed scheme does have a significant improvement on the pipelined ADC's performance.

This thesis also discusses the circuit implementation of a digital background calibration processor for a 12-bit 100MS/s pipelined ADC prototype with open-loop residue amplifiers. The simulation results of this prototype show a great improvement on the pipelined ADC's performance with the digital calibration technique.