使用共用傳導層傳送晶片間多重信號機制

Abstract

本篇論文提出一個新型三維積體電路晶片間連接的應用架構，使用共用傳導層傳送晶片間多重信號機制，使用導電介質如導電膠，將晶片與晶片黏合並形成傳導層。與其它三維積體電路晶片使用無線或有線傳輸的架構有比較近的通訊距離，此篇論文設計的距離為2微米。較短的通訊距離也就是共用傳導層厚度越薄，意味著有較好的抵抗鄰近雜訊干擾能力也能增加高密度連線的數量。我們也設計十字標記對準機制來偵測位移誤差，在上下區塊的晶片上設計傳送端與接收端的中繼器，可以量測出訊號完整性。且此晶片也用來驗證共用傳導層之間的電阻模型。 共用傳導層傳送晶片間多重信號機制操作在2Gbps時能達到0.18pJ/bit能量效率，使用台積電 0.18微米1P6M CMOS 製程來實現與驗證此新型的三維晶片傳輸架構。

A broadcast interconnects method for 3D-IC applications is implemented by using common conduction layer. Die-to-Die Multi-signaling communication mechanism with common conduction layer has shorter communication distance. Compared with wireless or wire interconnect. Our communication distance is 2um. The shorter distance means that it can resist the neighborhood noise and increase the IO density for packaging. Moreover, chip thinning, together with device scaling, will further improve the density and performance of the vertical I/Os. As a result, because of the larger I/O count possible in 3D integration and the short length of the interconnections, it is expected that the vertical I/Os between stacked chips will be able to provide the high data bandwidth required by Moore’s law with the benefit of low-power signaling. We also use alignment method for detecting position error. In our design, a buffer stage may be needed between the circuit blocks in different layers, since common conduction layer usually have a much larger Parasitic Resistance than interconnects of circuits. This interconnect has energy efficiency of 0.18 pJ/bit at 2Gbps. The proposed broadcast interconnects method is implemented in TSMC 0.18um process for demonstration of this architecture.