20 MHz 訊號頻寬 640 MHz 連續時間三角積分類比數位轉換器設計

Abstract

這篇論文中，基本的三角積分類比數位轉換器將被說明並討論，同時連續 時間三角積分類比數位轉換器的設計流程將被呈現。之後，一個使用台積電0.18 微米互補式金氧半導體製程實現的三階四位元連續時間積分類比數位轉換器將 被呈現。此轉換器操作在640 MHz 取樣頻率以及20 MHz 的訊號頻帶。模擬的訊 號失真雜訊比為52.82dB 而動態輸入範圍為50 dB。在1.8V 的電源供給下的功 率消耗為20.50 毫瓦。

In this thesis, the background of ΣΔ modulator (SDM) is illustrated and discussed. The design flow of the continuous-time (CT) ΣΔ modulator is presented. Then, a 3rd- order 4-bit continuous-time (CT) ΣΔ modulator is presented and implemented in TSMC 0.18 μm CMOS process. The modulator operates at 640 MHZ clock frequency and the signal bandwidth is 20 MHz. The post simulated SNDR is 52.82dB and the dynamic range is 50dB. The power consumption is 20.5mW at 1.8V supply voltage.