應用於24 GHz 連續調頻雷達之低功耗壓控振盪器與低閃爍雜訊次諧波混頻器

Abstract

本論文提出兩個應用在 24 GHz 車用雷達系統收發機中的射頻前端電路： 8 GHz 新式壓控振盪器與16 GHz 低閃爍雜訊次諧波混頻器，均以TSMC 0.18 μm 1P6M CMOS 製程實現。 8 GHz 新式壓控振盪器，是以電流再利用為主要架構，透過串疊型式的交連 耦合對以及額外引入的可調式小尺寸交連耦合對，將差動兩端的電晶體各別給予 不同的偏壓電壓以及偏壓電流，藉此平衡差動兩端不匹配的電晶體轉導，改善原 本電流再利用架構之差動兩端輸出振幅不匹配的問題，可以將差動振幅精準匹配 至僅有0.15%的誤差。其相位雜訊在1 MHz 位移時為-114 dBc/Hz，輸出功率最 高為-2dBm，調頻範圍從7.707 GHz 至8.047 GHz，功耗為2.995 mW，FoM 可達 -187.1 dBc/Hz。 16 GHz 低閃爍雜訊次諧波混頻器，以水平式次諧波混頻器為基礎電路架 構，採取大尺寸 PMOS 電晶體組成開關級，並利用折疊架構將轉導級與開關級 之偏壓電流分開設計，得以降低次諧波混頻器中開關級電晶體的直流電流大小， 最後再加入電流補償技術，使開關級直流電流可以進一步縮小，將閃爍雜訊轉角 頻率由原本8 MHz 降低至200 KHz。其轉換增益為6.573 dB，IP1dB 為-14 dBm， IIP3 為-4.08 dBm，白色雜訊指數為12.7 dB，直流功耗17.02 mW。

The thesis proposes two RF front-end circuits: a 8GHz novel VCO and a 16 GHz low flicker noise sub-harmonic mixer (SHM). Both can apply to 24GHz FMCW radar applications and were fabricated with TSMC 0.18μm 1P6M process. The proposed VCO adopts current-reused structure with a cascode cross-coupled pair and an additional tunable small size cross-coupled pair, giving different bias voltage and current to the differential MOSFETs, to reduce the inherently differential transconductance mismatch with current-reused VCO. This strategy can exactly balance the differential amplitude with only 0.15% error. The phase noise equals to -114 dBc/Hz at 1MHz offset while consuming 2.995 mW and achieving a tuning range from 7.707 to 8.047GHz. The proposed SHM is based on SHM structure with PMOS switch stage, applying folded skill to separately design the DC current in switch stage form transconductance stage, to reduce the DC current in switch stage. In the end, this chip uses the current bleeding technique to more reduce the DC current. The flicker noise corner then could be restrained to 200 kHz from original 8 MHz. The Conversion Gain is 6.573 dB with IP1dB of -14 dBm, IIP3 of -4.08 dBm and White Noise Figure of 12.7 dB while consuming 17.02 mW。