應用於無線通訊系統之低參考邊頻低相位雜訊頻率合成器

Abstract

本論文提出降低參考邊頻和低相位雜訊技術之整數型頻率合成器並且實現較寬的迴路頻寬同時達到低相位雜訊。實現了三種不同架構的整數型頻率合成器，這些電路皆應用於類比電視以及WIMAX行動通訊上。 在射頻系統上，頻率合成器的設計仍然是最具有挑戰性議題之ㄧ。因為它必須要達到非常嚴格要求，例如:穩定時間(settling time)、相位雜訊(phase noise)、參考愧入 (reference feedthrough)，又被稱作參考邊頻 (reference spur) ，．．等。在設計頻率合成器中，有幾個取捨(trade-off)會出現。首先，穩定時間長短主要取決於迴路頻寬 (loop bandwidth) 大小。同時因為考量迴路的穩定性，迴路頻寬會被限制在大約1/10的參考頻率。接著，壓控振盪器的相位雜訊只有在小於迴路頻寬時才會被回授的迴路所降低。最後，我們需要縮小迴路頻寬來降低參考邊頻。為了解決這些取捨，我們設計出幾種新的架構採取隨機脈寬匹配和次取樣電荷泵技術，隨機選擇相位頻率偵測器等概念來降低參考邊頻和相位雜訊的鎖相迴路。 我們敘述了三種整數型頻率合成器。其中第一個是利用隨機脈寬匹配和次採樣電荷泵技術以降低參考邊頻之頻率合成器。量測台積電90奈米CMOS技術之頻率合成器，顯示所提出的改良式電路參考邊頻被抑制為35分貝。這代表了我們所提出的新的分析技術的性能是可以被使用在整數型頻率合成器。另一個所提出的是利用隨機選擇相位頻率偵測器降低參考邊頻之頻率合成器。量測結果顯示: 壓控振盪器可調範圍從2500MHz到2700MHz，距離主訊號1MHz 偏移是-105分貝/赫茲的相位雜訊和參考邊頻為 -72分貝。 最後我們提出了低相位雜訊頻率合成器使用環式振盪器和多相位過採樣電荷泵技術。為了用簡單的設計來實現較好的相位雜訊，多相位過採樣電荷泵和窄波電路(one-shot)來降低壓控振盪器上控制電壓的漣波達到平滑的頻譜。量測台積電0.18微米CMOS技術之頻率合成器顯示出從15Hz到100 kHz偏移相位雜訊低於 -100分貝/赫茲和1MHz 偏移是-108分貝/赫茲的相位雜訊。

Spur reduction and low phase noise techniques are proposed that allow integer-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Three integer-N synthesizers are presented. These circuits are targeted for analog TV (ATV) and mobile WIMAX applications. Synthesizer design still remains one of the most challenge issues in the RF system because it must meet very stringent requirements, such as settling time, phase noise, reference feedthrough, etc. Several trade-offs exist in the synthesizer design. First, the settling time is largely determined by the loop bandwidth which is limited to approximately 1/10 of the reference frequency for the loop stability consideration. Second, the phase noise of the oscillator is reduced by the feedback loop only within the loop bandwidth. Finally, in order to suppress the reference spur, a small loop bandwidth is required. To solve all these trade-offs, we have proposed several new architectures adopting random pulsewidth matching, sub-sampling charge-pump, and randomly selected PFD to achieve low reference spur and low phase noise PLLs. The first one is the Random pulsewidth matching frequency synthesizer with sub-sampling charge pump. Measurement results of a prototype TSMC 90nm CMOS synthesizer show that the reference spur is suppressed by 35dB. These represent a new analysis technique that is useful in the characterization of integer-N frequency synthesizers. The other is a spur-reduction frequency synthesizer exploiting randomly selected PFD. The oscillator frequency is tunable between 2500~2700 MHz, phase noise is -105dBc/Hz @1 MHz offset, and the spurious tone is -72dBc. Finally, a low phase-noise ring VCO based frequency synthesizer with multi-phase over-sampling charge-pump is implemented. To achieve good phase noise performance with a simple design, the multi-phase over-sampling charge-pump and one-shot circuits to reduce ripples on the control voltage of the VCO provide a smooth spectrum. Measured results from a prototype by TSMC 0.18um CMOS technology show the phase noise below–100 dBc/Hz from 15 Hz to 100 KHz and–108 dBc/Hz with 1 MHz offset.