內建自我測試電路之管線化類比數位轉換器

Abstract

在本論文中，主要的目標是設計管線化類比數位轉換器的內建自我測試電路。我們提出一新的測試方，依照每一級的取樣保持電路的輸出信號的機率統計，去計算出管線化類比數位轉換器每一級的抵補誤差和增益誤差。首先，設計一8位元,50 MS/s,四級的管線化類比數位轉換器。並測量其靜態行為，積分型非線性誤差，微分型非線性誤差, 抵補誤差和增益誤差。然後，我們設計內建自我測試電路去量測管線化類比數位轉換器每一級的抵補誤差和增益誤差。把內建自我測試電路所測得的值和實際上管線化類比數位轉換器所量測的結果做比較。

In this thesis, our target is to design a built-in self-test circuit for the pipeline analog-to-digital converters. We propose a new approach. According to the probability of each stage sample-and-hold output signals, we can test the voltage offset error of each stage in pipeline analog-to-digital converters. First, we design a 8-bit, 50 MS/s and four stages pipeline analog-to-digital converters. And we measure the static characteristics which include differential nonlinearity error, integral nonlinearity error, offset error and gain error. Then, we measure offset error and gain error of each stage in pipeline analog-to-digital converters by built-in self-test circuits. Finally, we compare the result from built-in self-test circuits with the real value by measuring the pipeline analog-to-digital converters.