高速測試介面前端驅動電路設計

Abstract

傳統上測試機的前端驅動(PE)電路是將多個元件如參考電壓IC，驅動接收IC等晶片組合在一塊印刷電路板(PCB)上。元件之由匯流排傳輸，因而限制住它的速度且耗費較大的面積與成本。 在個論文中，我們以CMOS待測物為目標來實現PE電路。由於待測晶片工作頻率越來越快，所以我們必須使用高速的傳輸介面來傳送接收資料，如PVLECL標準或LVDS標準。在驅動器部份，我們使用tri-state buffer來達到規格所要的速度與驅動能力。我們使用窗型比較器來接收待測物的訊號；利用窗型比較器所產生的三個區間，來判斷訊號的正確與否。在動態負載部份，由於切換速度上的考量，我們仍用橋式二極體電路來做為電壓判斷電路，電流源部份則是由6-bit的數位訊號，來控制其流量。而電路中的參考電壓則由一個6-bit DAC加上一些解碼電路所提供。最後，我們以 TSMC 0.18um Mixed Signal 1p6m 1.8V/3.3V CMOS製程技術來實現我們整個設計的電路。並用Pre-simulation和Post-simulation來驗証設計的可能性。

Traditionally, the pin electronics (PE) card circuits of a tester consists of several components, such as reference voltage IC, driver/receiver IC and etc on a print circuit board (PCB). It uses the bus to connect all the components. Hence, the operation speed of PE is limited and the area of complete architecture is large. In this thesis, we target CMOS chip for our device under test circuit to design the PE card circuits. Owing to the operating frequency is more and more fast, we must use the high-speed interface to transmit or receive the data, such as low-voltage positive-reference emitter-coupled-logic (LVPECL) interface standard and low voltage differential signals (LVDS) interface standard. For driver part, we use tri-state buffer with parasitic inductance to achieve the speed requirement and the driving capabilities as the spec. We use the window comparator to receive the signal from the device under test (DUT). It will be divided into three voltage level ranges to compare whether the signal is valid or not. For dynamic load, due to the switching speed, we will still use the diode-bridge structure to be the voltage-comparison circuit. As for the current source, we use 6-bit digital signals to control how much current we need. And the all the reference voltages of this chip are provided by a 6-bit DAC and some decoders. Finally, the complete circuits have been designed and implemented by TSMC 0.18um Mixed Signal 1p6m 1.8V/3.3V process technology. Pre- and post-simulation will verify the feasibility of the design.