高能源效率與低查表之基本運算單元設計與實現

Abstract

在本論文中，我們提出了三個高能源效率與低查表之浮點數基本運算單元。第一個基本運算單元提供16位元指數、對數、倒數與開根號倒數之運算，第二個基本運算單元提供32位元指數、對數、倒數和開根號倒數之運算，第三個基本運算單元雙精準度設計，支援上述所有的運算及解析度。我們運用了一個分段線性近似法來計算16位元之運算；在32位元運算方面，我們提出了一個新的二階多項式近似法來計算指數與對數，而倒數與開根號倒數則是採用向前看牛頓–拉福生法來計算。所有的運算精確度都達到1ulp。提出的二階多項式近似法可減少12%之查表大小。本論文之基本運算單元使用TSMC 0.18um製程設計與實現，模擬顯示可操作在142 MHz時脈下。16位元基本運算單元所需之平均功耗為3.52mW，而32位元基本運算單元平均功耗為37.55mW；雙解析度之設計在16位元模式下平均功耗為5.74mW，32位元模式下之平均功耗為38.49mW。

In this work, three power-efficient floating-point elementary function units with small look-up tables are proposed. The first elementary function unit design supports the half-precision IEEE-754 floating-point standard and implement exponential, logarithm, reciprocal, and inverse square root operations. The second design supports the single-precision IEEE-754 floating-point standard and also implements exponential, logarithm, reciprocal, and inverse square root operations. The third design is a dual-precision eight-mode elementary function unit which supports all the above mentioned functions and precisions. The presented elementary function units employ a piecewise linear approximation scheme for 16-bit operations, a relaxed look-ahead Newton-Raphson method for the computation of 32-bit floating-point reciprocal and inverse square root, and a two-level polynomial approximation for 32-bit exponential and logarithm. All the operations achieve 1ulp accuracy. The proposed power-efficient elementary function units in TSMC 0.18um CMOS process can be operated at 142MHz. The proposed two-level polynomial approximation can reduce table size by 12% with respect to previously proposed techniques, without any accuracy loss. The average power of the 16-bit elementary function unit is 3.52mW, while that of 32-bit design is 37.55mW. The dual-precision eight-mode elementary function unit has 5.74mW in 16-bit mode and 38.49mW in 32-bit mode.