標題: 應用於3D圖學系統之高能源效率著色系統設計與實現
A Power-Efficient Rendering Engine Design and Implementation for 3D Graphics System
作者: 謝佳育
范倫達
資訊科學與工程研究所
關鍵字: 邊緣函式;內插;掃描轉換;深度測試;能源效率;edge function;interpolation;scan conversion;depth test;power efficiency
公開日期: 2010
摘要: 在本論文中,我們提出了一個高能源效率且具適應性掃描轉換機制及內嵌中心點為起始基底之邊界測試方法的著色引擎架構。在適應性掃描轉換機制的運作下,像素處理率(Pixel rate)被有效提升至少29%。在架構設計方面,為了降低硬體成本,主要提出兩個方法1) 針對三角形設定引擎之內插參數與內插值的初始設定,採用運算單元重複使用的技巧 2) 對於多組掃描轉換單元,採用內插參數共享共用的方式,結合此兩種方法可以使得硬體成本降低12.55%。另外,內插參數共享共用的機制除了能降低硬體成本,還能降低整體的系統功率消耗10%,進而提升能源效率10%。 著色引擎的架構已在TSMC 0.18um 製程下設計與實現。在100MHz的操作頻率下其像素處理率為27Mpixel/s及功率消耗為14.55mW,達到1.85MPixels/s*mW的能源效率。
In this thesis, a power-efficient rendering engine using an adaptive scan conversion mechanism embedded with the proposed central start-point based boundary-edge test is presented. By applying the adaptive mechanism, the pixel rate can be enhanced. In the simulation level, the average pixel rate can be enhanced by 29%. In the architecture level, the arithmetic logic unit reuse scheme for generating interpolation parameter and initial value in the triangle setup and the shared interpolation parameter in the scan conversion are used to reduce the hardware resource. The overall hardware resource can be reduced by 12.55%. Besides, the power consumption using the shared data mechanism can be reduced by 10% and the power efficiency can be enhanced by 10%. The proposed rendering engine architecture implemented in TSMC 0.18um CMOS process provides 27MPixels at 100MHz with power consumption of 14.55mW, and achieves the power efficiency of 1.85MPixels/s*mW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079755544
http://hdl.handle.net/11536/45889
顯示於類別:畢業論文