SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	JOU, SJ	en_US
dc.contributor.author	SHEN, WZ	en_US
dc.contributor.author	JEN, CW	en_US
dc.contributor.author	LEE, CL	en_US
dc.date.accessioned	2014-12-08T15:06:02Z	-
dc.date.available	2014-12-08T15:06:02Z	-
dc.date.issued	1987-12-01	en_US
dc.identifier.issn	0956-3768	en_US
dc.identifier.uri	http://hdl.handle.net/11536/4596	-
dc.language.iso	en_US	en_US
dc.title	SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT	en_US
dc.type	Article	en_US
dc.identifier.journal	IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS	en_US
dc.citation.volume	134	en_US
dc.citation.issue	6	en_US
dc.citation.spage	276	en_US
dc.citation.epage	283	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1987L218000004	-
dc.citation.woscount	0	-
顯示於類別：	期刊論文