寬頻分碼多重擷取系統之快速碼擷取及頻率偏移估測架構及其FPGA實現

Abstract

本篇論文的主要目的是設計及硬體實現一個寬頻分碼多重擷取系統上鏈通道的快速碼擷取(acquisition)及頻率偏移估測系統。在寬頻分碼多重擷取系統中，實體隨機擷取頻道(PRACH)的前序碼(preambles)通常被用來做傳輸初始同步的工作。由於特殊的前序碼結構，傳統匹配濾波器(matched filter)碼擷取架構需要很高的計算複雜度。在本篇論文中，吾人使用快速哈達馬轉換(Fast Hadamard Transform)的方法來解決這個問題，提出一可抵抗頻率偏移的非同調快速碼擷取架構。當碼同步達成時，我們使用以相關函數為基礎的頻率偏移估測方法。另外我們也使用雙重區塊(double dwell)搜尋技術來降低錯誤通報(false alarm)率。模擬的結果顯示出我們的設計在有頻率偏移的環境中也能有很高的碼擷取正確機率。最後我們使用VHDL硬體描述語言與Xilinx FPGA的設計流程來實現我們設計的系統。

In this thesis, we design and implement a fast acquisition and frequency offset estimation system for W-CDMA uplink transmission. In W-CDMA systems, preambles of the PRACH (physical random access channel) are used for initial synchronization. Due to the special preamble format, the conventional matched-filtering acquisition scheme requires high computational complexity. In this thesis, we employ a fast Hadamard transform (FHT) approach to solve the problem. A non-coherent acquisition architecture that can resist the frequency offset is developed. Once the code phase is acquired, we then apply a correlation-based method to estimate the frequency offset. To reduce the false alarm probability, we also use a double-threshold detection scheme. Simulations show that our design has high acquisition probability in presence of frequency offset. Finally, the proposed method is implemented using the VHDL hardware description language and the Xilinx FPGA design flow.