整合動態功率管理之平行資料路徑設計

Abstract

極長指令字組(VLIW)處理器是一種包含許多運算功能單元(functional unit)並可多重發派指令的處理器，許多VLIW處理器都可提供一些在平台式晶片系統設計(Platform-Based SoC Design)和可重置性的架構(Reconfigurable Architecture)中所需的基頻數位訊號處理(DSP)的運算[1-3]，如果使用VLIW處理器作為一個平台式晶片系統設計的中心微處理器，那麼某些DSP硬體的將可被微處理器所取代而減少硬體設計的複雜度；然而一般的VLIW處理器往往存在著低指令密度和低硬體使用率的缺點，而這些缺點也造成嚴重的玏率消秏，低指令密度會造成在管線暫存器的功率浪費，低硬體使用率則使得某些運算功能單元閒置而造成靜態功率的浪費。在這一篇論文中，我們針對低指令密度和低硬體使用率所造成的功率議題，挑選了闡控時脈和電壓分離這兩種動態功率管理技術，並整合在一顆相似於一具三發派指令的VLIW處理器的平行資料路徑；除此之外，我們也利用現有的EDA軟體，發展出一套可用來實現闡控時脈和電壓分離的設計流程，本論文中所有的設計和驗證都是使用UMC 0.18 um CMOS 製程參數來完成，而如同我們所預期的，在最後功率模擬分析的結果中發現，除了此平行資料路徑的功率消秏有明顯的改善，其效能和功率消秏之間也變得可微調，而具有此特性的資料路徑之VLIW處理器是更適合應用在一個平台式晶片系統設計和可重置性的架構。

Very long instruction word (VLIW) processor is a multi-issue processor with many functional units. In recent research [1-3], many VLIW processors can provide the functions of baseband digital signal processing (DSP) calculations such as discrete cosine transform (DCT), finite impulse response (FIR) filter, and motion estimation. These general purpose DSP calculations are very common in platform-based design and reconfigurable architecture for wireless communications and multi-media applications. So if a VLIW processor is applied as the microprocessor in platform-based design or reconfigurable architecture, some general purpose DSP blocks can be replaced by VLIW processor and the design complexity of hardware in platform-based design and reconfigurable architecture can be reduced. However, power dissipation in VLIW processor can be a serious problem due to the low code density and hardware utilization. In this thesis we applied dynamic power management techniques in the 16-bits parallel data path which is similar to a data path in a three-issue VLIW processor to reduce the overhead of power dissipation. Two dynamic power managements: clock gating and voltage separation are chosen since they are suitable for the parallel data path. Clock gating can reduce the power dissipation caused by low code density in pipeline registers and voltage separation can reduce power wastage in functional units that is caused by low hardware utilization. Furthermore, we also explored an appropriate design flow for these two power managements with current electronic design automation (EDA) tool. All the design and verification are completed with UMC 0.18 um process. Power analysis is accomplished with five test benches. The power dissipation of the parallel data path is successfully reduced and the power and performance of the data path become scalable as we expected. A VLIW processor with such a data path is provided as a good option for microprocessor in platform-based design and reconfigurable architecture.