高速數位電路之接地彈跳分析與電源完整性之設計與模擬

Abstract

近年數位電路工作頻率不斷的攀升與工作電壓的下降，使得電源傳輸網路(power distribution network, PDN)的阻抗設計日趨嚴格。本論文主要探討接地彈跳對電源完整性的影響，首先介紹接地彈跳(ground bounce noise, GBN)的成因，參考一些文獻並依據處理器工作方式的分析，定義出電源傳輸網路的低頻與高頻目標阻抗(target impedance)設計值，並以網路分析儀量測PDN阻抗與SIwave做模擬，分析比較PDN的阻抗分布，時域模擬則以ADS circuit simulator驗證目標阻抗的設計是否正確。接著分析解耦合電容的特性，找出適合的元件。也針對PCB的結構，分析電源傳輸線的迴路電感，試圖找出電感最低的佈線方法以減低GBN對電源造成的影響。最後建立出簡易的PDN解耦合半徑設計方法，找出解耦合電容放置的範圍。

In recent year, climbing frequency and descending supply voltage of digital circuit that cause power delivery network (PDN) design become more difficult. In this thesis, we discuss the effect of the ground bounce noise (GBN) and how it affects the power integrity (PI). At first, we introduce the phenomenon of the GBN and refer working pattern of CPU to analysis the impedance requirement. We try to define the target impedances of the low and high frequency of the PDN, and compare the distributions of the impedance that measured by network analyzer to one simulated by SIwave in frequency domain. Time domain simulation is also achieved by ADS circuit simulator to verify if the result is expected. Adding de-coupling capacitors is a typical way to suppress the GBN. We analyze the de-coupling characteristic of capacitors to find the appropriate component and the loop inductance of the PDN based on PCB stack-up. It helps us to find a design rule to decrease the loop inductance and the GBN on the power rail. Finally, we set up a method to design the de-coupling radius for the PDN to find out the placed range of the de-coupling capacitors.