標題: 可重設之低成本里德所羅門解碼器設計
A low-cost reconfigurable Reed-Solomon decoder
作者: 李昭宏
Jau-Hong Lee
紀翔峰
Hsiang-Feng Chi
電信工程研究所
關鍵字: 里德所羅門解碼器;Reed-Solomon decoder
公開日期: 2004
摘要: 在許多現行的通訊系統使用里德所羅門碼來更正錯誤並且要求硬體具有可重設能力。本論文目的即是實作了一個晶片面積小並且具有可重設功能的里德所羅門解碼器。在硬體上,我們將運算單元分為兩類,常數乘法器陣列單元以及單乘加處理器單元,其中錯誤位置多項式以及錯誤量的計算由單乘加處理器單元進行運算,而錯誤症計算以及錯誤位置尋找由常數乘法器陣列單元進行計算。在解碼過程中最重要也是最複雜的是屬於錯誤位置多項式的計算過程,在這方面我們所採用的演算法是inversion-less Berlekamp-Massey algorithm (iBMA)使得複雜的有限元素場除法運算可以被避免,因此晶片面積得以縮小;並且因為iBMA的運算量較一般常用的modified Euclidean algorithm(MEA)少,所以解碼過程所花去的週期也較少。此外,為了節省功率消耗當確定接收碼字為合法時,即停止所有解碼步驟且將輸入碼字直接輸出
The reconfigurability has become one of the necessary features for the state-of-the-art communication systems. This thesis is purposed to propose a low-cost reconfigurable Reed-Solomon decoder hardware architecture. In our architecture, we design two kinds of function units, a constant-GF multiplier array and a single GF-MAC (multiplier-and-accumulator) engine. The constant multiplier array is designed for syndrome calculation and Chien search, while the parallel MAC is used to calculate the error location polynomial and error magnitude. To save the hardware cost and execution cycles, we adopt inversion-less Berlekamp-Massey algorithm and use Fermat theorem to calculate reciprocal of finite field element. Besides, when receiving a valid codeword, we output the codeword directly without decoding in order to save the power consumption.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009113559
http://hdl.handle.net/11536/46457
顯示於類別:畢業論文