藉由兩階段矽鍺緩衝層以成長鍺磊晶層於矽基板上之研究

Abstract

根據摩爾定律，傳統的矽材料在小尺寸上(小於100奈米)開始遇到瓶頸，這時候三五族材料的特性如高電子遷移率開始被注意到，進而開始應用在元件，然而在為了降低生產成本上，磊晶三五族材料如砷化鎵在矽基板上開始被研究，為了磊晶出高品質的砷化鎵磊晶層，在文獻中發現砷化鎵/鍺/矽的結構，因為鍺和砷化鎵擁有幾乎相同的晶格常數和熱膨脹系數，在本論文中將會研究鍺磊晶層成長於矽基板上。 本實驗中藉由兩階段矽鍺緩衝層以成長鍺磊晶層於矽基板上，兩階段矽鍺緩衝層的結構是藉由控制每一層的矽鍺緩衝層中的鍺含量進而在磊晶層介面產生應力，由這介面產生的應力可以有效地阻擋在磊晶過成中往上衍生缺陷，最後在成長高品質的鍺磊晶層於這兩階段的矽鍺緩衝層。

According to Moore’s law, the device is scaling down below 100 nm, the performance of Si device is reaching its limitation. In the same time, the outstanding features of III-V material have attracted a lot of attention like higher electron mobility than Si and can potentially play a major role along with Si in future high speed devices. In order to reduce manufacturing costs, a heterogeneous integration of III/V compound materials (ex: GaAs) with Si platform is necessary. In literature, the high quality GeAs epilayers can be obtained by the structure of GaAs/Ge/Si buffer layer. The reason of using Ge as buffer layer is that the lattice constants and thermal expansion between Ge and GaAs are almost the same. In the thesis, the Ge grown epilayer on Si will be researched. The structure of two-step SixGe1-x buffer layers can be used for Ge epilayer grown on Si substrate. These two SixGe1-x buffer layers create the interface with stress to prevent the penetration of dislocations. Finally the high quality top Ge epilayer can be grown on the top of the two-step SixGe1-x buffer layers.