在矽基板及塑膠基板上以室溫製備含鋁摻雜氧化鋅的薄膜電晶體

Abstract

本論文主要對於製作於矽基板與塑膠基板上以含鋁摻雜之氧化鋅當作通道層的薄膜電晶體作研究。 在薄膜電晶體製作之前，本文首先對含鋁摻雜之氧化鋅薄膜進行物性分析，藉由直流濺渡系統沉積含鋁摻雜之氧化鋅，在沉積過程中調變氧氣流量，觀察薄膜之物理型態的改變。並探討在不同氧氣流量下共閘極含鋁摻雜之氧化鋅薄膜電晶體。得到其最佳化條件後，本研究在矽基板上製作定義出閘極的含鋁摻雜之氧化鋅薄膜電晶體並搭配高介電常數之閘極絕緣層，在線性區(VDS=0.5V)操作下，可得到臨界電壓、載子遷移率、次臨界斜率、電流開關比分別為0.39V、1.03cm2/V-s、532mV/decade、9.93×106。 在本研究中進一步探討將含鋁摻雜之氧化鋅薄膜電晶體製作於軟性基板上，由於塑膠基板之玻璃轉換溫度的限制，所有製程於低溫下完成。可得到線性區操作下之臨界電壓、載子遷移率、次臨界斜率、電流開關比分別為3.12V、1.62cm2/V-s、1.84V/decade、8.8×107。成功製作出薄膜電晶體之後，對其進行不同彎曲曲率測試以及固定曲率下彎曲次數的測試，皆能維持良好之電性。

This thesis focuses on ZnO:Al thin film transistors (AZO TFTs) fabricated on Si substrates and flexible substrates using a room-temperature process. Before fabricating the AZO TFT on Si substrates, we first analyzed the physical properties of AZO thin films deposited by DC sputtering with various oxygen flow rates. Then, common-gate AZO TFTs were fabricated with AZO channels deposited by various oxygen flow rates. The best AZO deposition condition with zero oxygen flow rate was chosen to fabricate the bottom-gate AZO TFTs with a high-□□gate insulator. In the linear region, the threshold voltage, mobility, sub-threshold swing, and current on to off ratio of the bottom-gate AZO TFT were 0.39V, 1.03cm2/V-s, 532mV/decade, and 9.93×106. Furthermore, we successfully fabricated AZO TFTs on a flexible polyimide substrate. Because of the limitation of glass transition temperature of flexible substrates, all processes were done at low temperature. In the linear region, the threshold voltage, mobility, sub-threshold swing, and current on to off ratio of the flexible AZO TFT were 3.12V, 1.62cm2/V-s, 1.84V/decade, and 8.8×107. The AZO TFT was subjected to bending tests measured at various bending curvatures (RC=10、30mm) and continuous bending cycles. The results show that AZO TFT can maintain good electrical properties after bending.