IEEE 802.16m 初始下行同步之數位訊號處理器實現

Abstract

本篇論文研究方向為針對IEEE 802.16m中初始下行同步裡，實作於數位訊號處理平台上的議題探討。 當一個行動電話開始要進入網路的時候，我們必須與基地台做初始的同步。在初始的同步中，包含了符元時間偏移、載波偏移和前置符元序號(preamble index)需要同步估測。我們利用前置符元的功率較一般資料符元(data symbol)大的特性做功率移動累加，藉由找到累加結果的峰值來估測前置符元的起始位置。由此起始位置向後推算一個符元長度以當作我們所估測出來的前置符元，而與真實的前置符元存在一個相位性錯誤(phase error)。我們利用此估測出來的前置符元推導其近似最大可能性估測(quasi maximum likelihood)以求得小數部分載波偏移和導出前置符元的通道估測的式子。我們在頻域上將此通道估測的式子經由估測出來的小數部分載波偏移補償之後，代入由合理範圍的整數部分載波偏移和不同的前置符元而得到的通道脈衝響應。再計算這些通道脈衝響應不同的精準符碼時間偏移序號64 點功率和並且選出最大的那一個，其所在的整數部分載波偏移、前置符元和精準符碼時間偏移序號即為此聯合估測的結果。 接著，我們把此演算法實作於浮點運算與定點運算，以及比較兩者的效能。最後，把定點運算實現於數位訊號處理平台，並且最佳化我們的程式速度，減少運算複雜度，雖然定點運算會早成效能的衰減，但是結果依然可以接受。

In this thesis, the research focus on initial downlink synchronization of IEEE 802.16m, and discuss the implementation issue of DSP. When a mobile station entering to the network, it needs to perform initial synchronization, including of symbol timing offset, carrier frequency offset and preamble index. We utilize the trait which the power of preamble is larger than it of the common data symbol to compute the moving power sum, and then estimate the left boundary of preamble by finding out the peak value of moving power sum. A symbol period from this estimated boundary is regarded as the estimated preamble, which has a phase noise with the exact preamble. We derive the quasi maximum likelihood estimation from the likelihood function of the estimated preamble to obtain fractional carrier frequency offset (FCFO) and the formula of channel estimation. After compensating the estimated fractional carrier frequency offset to the formula of channel estimation, we substitute several reasonable integral carrier frequency offsets (ICFOs) and primary advanced preambles (PA-Preambles) into this formula and obtain channel impulse responses (CIRs). After that, we compute different fine timing offset index 64-points power sum of these CIRs and find out the peak value whose ICFO, PA-Preamble index, and fine timing offset index are regarded as the result of the joint estimation. In order to compare the performance, we implement the algorithm into the floating-point and fixed-point version. In the end, we modified the fixed-point version on the digital signal processor platform, and optimize the speed of our programs to reduce operation complexity. Although the performance is degraded because of fixed-point modification, the results still can be accepted.