適用於三維圖形應用之無唯讀記憶體對數函式單元設計

Abstract

近年來三維圖形應用被大幅地使用在可攜式裝置上，如智慧型手機以及平板電腦，三維圖形處理器相較於一般的處理器使用了大量的且繁重的算術運算，像是除法、倒數、開根號、平方以及次冪。而這些繁重的運算所花的時間佔據所有處理時間百分之七十七[1] ，所以為了完成這些繁重的運算將會消耗大部分的能量，因此針對這些複雜的函數應該盡可能地去降低它們的能量消耗。 我們使用對數演算法來簡化算術運算，可以將乘法除法簡化成加法以及減法，對數演算法有很多實現的方式，大致上可以分為三種，第一種為遞迴函數求解，雖然可以得到較佳的準確度，但是需要花費多個延遲時間，而不適合應用在即時三維圖形應用上，第二種為查表法，雖然可以快速的求解，但是表的大小決定了準確度，當準確度需求越高則表越大，第三種為平移和加法,避免了需要大量時序或需要表與乘法的方法，所以我們採用了第三種平移和加法來實現對數演算法。並且提出一個實現對數演算法的方法，以及根據應用可容忍的錯誤率來產生一組對數函式單元的設計流程。在實現演算法的部分跟以往實現演算法的方法比較，可以改善信號雜訊大概2.7db，而設計流程可以簡硬體百分之三十一。

In recent years, real-time three-dimensional (3D) graphics applications have been widely used in mobile devices such as smartphones and tablet PCs. 3D graphics processors require heavy arithmetic calculations such as division, reciprocal, square root, square, and power operations. In contrast to general processors, these heavy arithmetic functions require 77% of the total processing time [1], and these functions consume most of the computing power and clock cycles in real-time 3D graphics systems. To reduce power consumption, the clock cycles used by these complex functions should be reduced as much as possible. We use logarithmic number systems to simplify the arithmetic operations: multiplications/divisions can be simplified to additions/subtractions. Logarithmic conversion methods can be classified into three categories: 1) digit recurrence, with the highest accuracy but long latency, and therefore, they are not suitable for real time 3D graphics systems; 2) lookup tables, with fast convergence, but the table size determines the accuracy and to get more accuracy, the table size should be large; and 3) shift-and-add methods, which just use simple shift and add to perform logarithmic conversions. The third implementation can avoid long latency and use of tables; therefore, we use the shift-and-add base to implement logarithmic algorithms. We propose a method to approximate the logarithmic curve and a design flow that generates a logarithmic functional unit on the basis of error tolerance. The proposed approximation method can improve the signal-to-noise ratio by about 2.7 db, and the proposed design flow can simplify hardware complexity by 31%.