0.5-V低抖動相位注入鎖相迴路之設計

Abstract

本篇論文提出二個相位注入鎖相迴路，其著重在低抖動及低電壓的設計。第一個版本的鎖相迴路採用多頻帶的壓控振盪器搭配相位注入的技巧。藉由相位注入的機制，在每個參考時脈週期，振盪器輸出的零交越點會被校正。第一版的鎖相迴路以UMC 55 nm 1P10M CMOS製程製作，操作在1.5 GHz時，功率消耗為2.4 mW，供應電壓為0.5 V，輸出峰對峰值的抖動為13.3 ps，晶片核心部分面積為0.014 mm2。第二版的鎖相迴路採用相位內差電路透過調整相位注入比例來控制迴路操作在鎖相迴路，延遲鎖相迴路，或是二種混合模式。透過調整相位注入比例可以在不同的雜訊環境下最佳化抖動的性能。第二版的鎖相迴路以TSMC 90 nm 1P9M CMOS製程模擬，操作在1.25 GHz時，功率消耗為2.2 mW。輸出峰對峰值的抖動為6.5 ps。

This thesis proposes two phase-injection phase-locked loops (PLLs), which focus on low-jitter and low-voltage design. The first version of PLL employs a multi-band voltage-controlled oscillator (VCO) with phase-injection. With the phase-injection mechanism, the zero-crossings of the VCO output are corrected in each reference clock cycle. The first version of PLL is fabricated in UMC 55 nm 1P10M CMOS process. The output jitter is 13.3 ps (peak-to-peak) at 1.5 GHz and the power consumption is 2.4 mW with a supply voltage of 0.5 V. The active die area is 0.014 mm2. The second version of PLL employs an interpolator to configure the loop to operate as a PLL, DLL, or a mixture of the two depending on the injection ratio. Tuning the injection ratio can optimize the jitter performance under different noise environment. The second version of PLL is simulated in TSMC 90 nm 1P9M CMOS process. The output jitter is 6.5 ps (peak-to-peak) at 1.25 GHz and the power consumption is 2.2 mW.