考慮資料稀疏性之低功率多變數式擬群加密器

Abstract

傳統多維分佈的二次多項式擬群加密系統使用需要大面積且耗能的高平行化架構來得到最大的加密速度。本篇論文提出了一個小巧的二次多項式擬群加密系統架構，藉由輸入資料預前抓取與加入收集器方法可有效降地系統面積與功率消耗，加入此方法的系統架構可達到面積功率最佳化亦保有系統的通訊頻寬。與傳統平行化硬體架構相比，本論文所提出架構，其面積降低三十倍。此系統所實現的加密系統在Xilinx Virtex-5 FPGA上系統頻率為172.62 MHz可達到有效通訊頻寬為50.21 Mbps，在Altera Cyclone-IV上系統頻率為101.53 MHz可達有效通訊頻寬為29.54 Mbps。以ASIC方式進行實現所提出之架構，讓外部SRAM以平行方式做處理，其有效通訊頻寬可以達到1.14 Gbps。而當輸入資料的資料為零位元值之稀疏程度到達66%，整體運算系統使用輸入資料預前抓取與加入收集器等方法的動態功率消耗可節省7%，實際在Altera DE2-115板子上以50MHz系統頻率量測100萬筆資料，所得系統有效通訊頻寬為14.41 Mbps。因此，本論文所時實現的系統在擁有足夠的系統安全度及加密速度下，應用於可攜式加密裝置上， 並且增加電池壽命。

Conventional Multivariate Quadratic Quasi-group encryption with fully paral-lel processing architectures required large area and high power consumption with reasonable encryption throughput. A compact MQQ encryption architecture based on a quasi-group string was proposed in the thesis. The data prefetch scheme and additional classifiers processing were proposed to reduce chip area and power consumption. The area and power consumption of the proposed hardware architecture was optimized while sustaining encryption throughput. Comparing with traditional fully paralleling architectural, area of this design had 30 times smaller. The implementation results achieved effective encryption throughput of 50.21 Mbps on a Xilinx Virtex-5 FPGA at 172.62 MHz clock rate and 29.54 Mbps on Altera Cyclone-IV FPGA at 101.53 MHz clock rate. The dynamical power of this architecture could save 7% while the input test pattern contains 66% zero bits. With parallel processing of ex-ternal SRAMs, the effective throughput of ASIC mapping architecture could achieve 1.14 Gbps. The system evaluation could reach 14.41 Mbps at 50 MHz clock rate with one million input test patterns on Altera DE2-115 FPGA board. Hence, the design system can have more battery life with enough security and encryption throughput to be used on portable crypto device.